Connie C. Yoha

Array ( [id] => 20739484 [patent_doc_number] => 20260148791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-28 [patent_title] => PARALLEL OPERATIONS IN COMPUTE SYSTEMS [patent_app_type] => utility [patent_app_number] => 19/397790 [patent_app_country] => US [patent_app_date] => 2025-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19397790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20196561 [patent_doc_number] => 20250273271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 19/012078 [patent_app_country] => US [patent_app_date] => 2025-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19012078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19852815 [patent_doc_number] => 20250098166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH A THREE-DIMENSIONAL STACKED MEMORY CELL STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/964178 [patent_app_country] => US [patent_app_date] => 2024-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18964178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19803744 [patent_doc_number] => 20250069669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => WRITE PERFORMANCE OPTIMIZATION FOR ERASE ON DEMAND [patent_app_type] => utility [patent_app_number] => 18/937365 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18937365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19986760 [patent_doc_number] => 20250124982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => APPARATUS AND METHODS INCLUDING SOURCE GATES [patent_app_type] => utility [patent_app_number] => 18/932143 [patent_app_country] => US [patent_app_date] => 2024-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19757785 [patent_doc_number] => 20250046350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => METHODS FOR EFFICIENT 3D SRAM-BASED COMPUTE-IN-MEMORY [patent_app_type] => utility [patent_app_number] => 18/920013 [patent_app_country] => US [patent_app_date] => 2024-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18920013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19749199 [patent_doc_number] => 20250037764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => ReRAM MEMORY ARRAY THAT INCLUDES ReRAM MEMORY CELLS HAVING A ReRAM DEVICE AND TWO SERIES-CONNECTED SELECT TRANSISTORS THAT CAN BE SELECTED FOR PROGRAMMING [patent_app_type] => utility [patent_app_number] => 18/913162 [patent_app_country] => US [patent_app_date] => 2024-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20422837 [patent_doc_number] => 20250384922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => EVALUATION CIRCUIT FOR STATIC RANDOM-ACCESS MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/889380 [patent_app_country] => US [patent_app_date] => 2024-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18889380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19712359 [patent_doc_number] => 20250022501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => BALANCED NEGATIVE BITLINE VOLTAGE FOR A WRITE ASSIST CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/773284 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19531496 [patent_doc_number] => 20240355398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => BIAS CONTROL FOR MEMORY CELLS WITH MULTIPLE GATE ELECTRODES [patent_app_type] => utility [patent_app_number] => 18/758483 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19893040 [patent_doc_number] => 20250118352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/746447 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19893041 [patent_doc_number] => 20250118353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/746473 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19500121 [patent_doc_number] => 20240339139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE INCLUDING MEMORY STRING AND PLURALITY OF SELECT TRANSITSTORS AND METHOD INCLUDING A WRITE OPERATION [patent_app_type] => utility [patent_app_number] => 18/746238 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 466 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19986742 [patent_doc_number] => 20250124964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => APPARATUSES AND METHODS FOR PER ROW ACTIVATION COUNTER TESTING [patent_app_type] => utility [patent_app_number] => 18/745068 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19435736 [patent_doc_number] => 20240304234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => MEMORY DEVICE AND METHOD OF CONTROLLING ROW HAMMER [patent_app_type] => utility [patent_app_number] => 18/669714 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20898868 [patent_doc_number] => 12706136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-11 [patent_title] => Managing memory based on access duration [patent_app_type] => utility [patent_app_number] => 18/656156 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19559623 [patent_doc_number] => 20240371415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => METHODS FOR EFFICIENT 3D SRAM-BASED COMPUTE-IN-MEMORY [patent_app_type] => utility [patent_app_number] => 18/653788 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19384850 [patent_doc_number] => 20240274720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => CONCURRENT COMPENSATION IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/642326 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20313523 [patent_doc_number] => 20250331152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => COMPACT GAIN CELL [patent_app_type] => utility [patent_app_number] => 18/637652 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19363933 [patent_doc_number] => 20240265967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => NON-VOLATILE CONTENT ADDRESSABLE MEMORY DEVICE HAVING SIMPLE CELL CONFIGURATION AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/621853 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621853 [rel_patent_id] =>[rel_patent_doc_number] =>)