Search

Connie C. Yoha

Examiner (ID: 10490, Phone: (571)272-1799 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2827, 2825, 2818
Total Applications
1355
Issued Applications
1259
Pending Applications
46
Abandoned Applications
62

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17295186 [patent_doc_number] => 20210391025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => ENHANCED MULTISTATE VERIFY TECHNIQUES IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/899965 [patent_app_country] => US [patent_app_date] => 2020-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899965 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899965
Enhanced multistate verify techniques in a memory device Jun 11, 2020 Issued
Array ( [id] => 16781438 [patent_doc_number] => 20210118517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/894035 [patent_app_country] => US [patent_app_date] => 2020-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16894035 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/894035
MEMORY DEVICE Jun 4, 2020 Abandoned
Array ( [id] => 17469974 [patent_doc_number] => 11276456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Systems and methods for capture and replacement of hammered word line address [patent_app_type] => utility [patent_app_number] => 16/887065 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7979 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16887065 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/887065
Systems and methods for capture and replacement of hammered word line address May 28, 2020 Issued
Array ( [id] => 16668213 [patent_doc_number] => 10937466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Semiconductor package with clock sharing and electronic system including the same [patent_app_type] => utility [patent_app_number] => 16/880506 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 12007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880506 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/880506
Semiconductor package with clock sharing and electronic system including the same May 20, 2020 Issued
Array ( [id] => 16471426 [patent_doc_number] => 20200372964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => DATA TRANSFER CIRCUIT, ELECTRONIC COMPONENT, ELECTRONIC APPARATUS, AND VEHICLE [patent_app_type] => utility [patent_app_number] => 16/879916 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16879916 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/879916
Data transfer circuit, electronic component, electronic apparatus, and vehicle May 20, 2020 Issued
Array ( [id] => 16781408 [patent_doc_number] => 20210118487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => FLASH MEMORY DEVICE AND COMPUTING DEVICE INCLUDING FLASH MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/871815 [patent_app_country] => US [patent_app_date] => 2020-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871815 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/871815
Flash memory device and computing device including flash memory cells May 10, 2020 Issued
Array ( [id] => 17217497 [patent_doc_number] => 20210350835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => CONDITIONAL WRITE BACK SCHEME FOR MEMORY [patent_app_type] => utility [patent_app_number] => 16/867649 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16867649 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/867649
Conditional write back scheme for memory May 5, 2020 Issued
Array ( [id] => 16256525 [patent_doc_number] => 20200265900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => Method for Reading Data Stored in a Flash Memory According to a Threshold Voltage Distribution and Memory Controller and System Thereof [patent_app_type] => utility [patent_app_number] => 16/865573 [patent_app_country] => US [patent_app_date] => 2020-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16865573 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/865573
Method for reading data stored in a flash memory according to a voltage characteristic and memory controller thereof May 3, 2020 Issued
Array ( [id] => 17606896 [patent_doc_number] => 11335388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Semiconductor memory device including memory string and plurality of select transistors and method including a write operation [patent_app_type] => utility [patent_app_number] => 16/862893 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862893 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/862893
Semiconductor memory device including memory string and plurality of select transistors and method including a write operation Apr 29, 2020 Issued
Array ( [id] => 16660365 [patent_doc_number] => 20210057002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SECURE MECHANISM IN SECURITY CHIP [patent_app_type] => utility [patent_app_number] => 16/850788 [patent_app_country] => US [patent_app_date] => 2020-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16850788 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/850788
Memory device having security command decoder and security logic circuitry performing encryption/decryption commands from a requesting host Apr 15, 2020 Issued
Array ( [id] => 17477090 [patent_doc_number] => 20220084594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => TERNARY MEMORY CELL FOR LOGIC-IN-MEMORY AND MEMORY DEVICE COMPRISING SAME [patent_app_type] => utility [patent_app_number] => 17/424492 [patent_app_country] => US [patent_app_date] => 2020-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17424492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/424492
Ternary memory cell for logic-in-memory and memory device comprising same Apr 2, 2020 Issued
Array ( [id] => 17637906 [patent_doc_number] => 11348635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Memory cell biasing techniques during a read operation [patent_app_type] => utility [patent_app_number] => 16/834941 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 17799 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834941 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834941
Memory cell biasing techniques during a read operation Mar 29, 2020 Issued
Array ( [id] => 18000712 [patent_doc_number] => 11501823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Semiconductor memory devices including sense amplifier adjusted based on error information [patent_app_type] => utility [patent_app_number] => 16/812850 [patent_app_country] => US [patent_app_date] => 2020-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 41 [patent_no_of_words] => 15673 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16812850 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/812850
Semiconductor memory devices including sense amplifier adjusted based on error information Mar 8, 2020 Issued
Array ( [id] => 17395713 [patent_doc_number] => 11244735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Systems and methods for program verification on a memory system [patent_app_type] => utility [patent_app_number] => 16/793749 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/793749
Systems and methods for program verification on a memory system Feb 17, 2020 Issued
Array ( [id] => 16000393 [patent_doc_number] => 20200176067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => ERASE OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/787199 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16787199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/787199
Memory device and method of performing erase and erase verify operations Feb 10, 2020 Issued
Array ( [id] => 16995159 [patent_doc_number] => 20210233579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => SYSTEM AND METHOD FOR COMPENSATING FOR SDRAM SIGNAL TIMING DRIFT THROUGH PERIODIC WRITE TRAINING [patent_app_type] => utility [patent_app_number] => 16/752442 [patent_app_country] => US [patent_app_date] => 2020-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752442 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/752442
System and method for compensating for SDRAM signal timing drift through periodic write training Jan 23, 2020 Issued
Array ( [id] => 17092681 [patent_doc_number] => 11120875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Nonvolatile semiconductor memory device with a plurality of memory blocks with memory strings and a shared block decoder to allow the number of selection signals to be reduced [patent_app_type] => utility [patent_app_number] => 16/752230 [patent_app_country] => US [patent_app_date] => 2020-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 14275 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752230 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/752230
Nonvolatile semiconductor memory device with a plurality of memory blocks with memory strings and a shared block decoder to allow the number of selection signals to be reduced Jan 23, 2020 Issued
Array ( [id] => 16936088 [patent_doc_number] => 20210201977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => BALANCED NEGATIVE BITLINE VOLTAGE FOR A WRITE ASSIST CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/731357 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/731357
Balanced negative bitline voltage for a write assist circuit Dec 30, 2019 Issued
Array ( [id] => 16920112 [patent_doc_number] => 20210193204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => LOW VARIABILITY REFERENCE PARAMETER GENERATION FOR MAGNETIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 16/720058 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720058 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720058
Low variability reference parameter generation for magnetic random access memory Dec 18, 2019 Issued
Array ( [id] => 15840957 [patent_doc_number] => 20200135761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => SEMICONDUCTOR MEMORY DEVICE HAVING A CHANNEL STRUCTURE VERTICALLY PASSING THROUGH A PLURALITY OF MEMORY LAYERS AND HAVING MEMORY CELL BLOCKS AND DUMMY MEMORY CELL BLOCKS [patent_app_type] => utility [patent_app_number] => 16/719089 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719089 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719089
Semiconductor memory device having a channel structure vertically passing through a plurality of memory layers and having memory cell blocks and dummy memory cell blocks Dec 17, 2019 Issued
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