Search

Connie C. Yoha

Examiner (ID: 10490, Phone: (571)272-1799 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2827, 2825, 2818
Total Applications
1355
Issued Applications
1259
Pending Applications
46
Abandoned Applications
62

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15717117 [patent_doc_number] => 20200105326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => Defect Propagation Structure and Mechanism for Magnetic Memory [patent_app_type] => utility [patent_app_number] => 16/147283 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147283 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147283
Defect propagation structure and mechanism for magnetic memory Sep 27, 2018 Issued
Array ( [id] => 16356229 [patent_doc_number] => 10796746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Frequency synthesis for memory input-output operations [patent_app_type] => utility [patent_app_number] => 16/138621 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/138621
Frequency synthesis for memory input-output operations Sep 20, 2018 Issued
Array ( [id] => 14903755 [patent_doc_number] => 20190295643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/128439 [patent_app_country] => US [patent_app_date] => 2018-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16128439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/128439
SEMICONDUCTOR MEMORY DEVICE Sep 10, 2018 Abandoned
Array ( [id] => 18262908 [patent_doc_number] => 11610615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Lookup table circuit comprising a programmable logic device having a selection circuit connected to a memory cell array and separated from a path of a read circuit [patent_app_type] => utility [patent_app_number] => 17/274099 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 11314 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17274099 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/274099
Lookup table circuit comprising a programmable logic device having a selection circuit connected to a memory cell array and separated from a path of a read circuit Sep 6, 2018 Issued
Array ( [id] => 16372164 [patent_doc_number] => 10803930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Memory system including a memory controller and error correction circuit for reading multi-bit data and for detecting and correcting read data errors [patent_app_type] => utility [patent_app_number] => 16/123123 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 13135 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16123123 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/123123
Memory system including a memory controller and error correction circuit for reading multi-bit data and for detecting and correcting read data errors Sep 5, 2018 Issued
Array ( [id] => 16308480 [patent_doc_number] => 10777285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Memory system capable of preventing read fail, including reading a second memory block through a dummy read operation, when an erase operation is performed to a first memory block, and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/121147 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 13163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121147 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121147
Memory system capable of preventing read fail, including reading a second memory block through a dummy read operation, when an erase operation is performed to a first memory block, and operating method thereof Sep 3, 2018 Issued
Array ( [id] => 15597065 [patent_doc_number] => 20200075067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => APPARATUSES AND METHOD FOR TRIMMING INPUT BUFFERS BASED ON IDENTIFIED MISMATCHES [patent_app_type] => utility [patent_app_number] => 16/121325 [patent_app_country] => US [patent_app_date] => 2018-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121325 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121325
Apparatuses and method for trimming input buffers based on identified mismatches Sep 3, 2018 Issued
Array ( [id] => 14874687 [patent_doc_number] => 20190287585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => MEMORY INTERFACE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/114177 [patent_app_country] => US [patent_app_date] => 2018-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16114177 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/114177
Memory interface and memory system including plurality of delay adjustment circuits shared by memory read and write circuits for adjusting the timing of read and write data signals Aug 26, 2018 Issued
Array ( [id] => 13995311 [patent_doc_number] => 20190066813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => TESTING MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/109185 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16109185 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/109185
Testing memory cells by allocating an access value to a memory access and granting an access credit Aug 21, 2018 Issued
Array ( [id] => 15138985 [patent_doc_number] => 10482974 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-19 [patent_title] => Operation of a memory device during programming [patent_app_type] => utility [patent_app_number] => 16/106185 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106185 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106185
Operation of a memory device during programming Aug 20, 2018 Issued
Array ( [id] => 15502863 [patent_doc_number] => 20200051620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => MEMORY DEVICE AND PROGRAMMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/057871 [patent_app_country] => US [patent_app_date] => 2018-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16057871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/057871
Memory device and programming method of multi-level cell (MLC) Aug 7, 2018 Issued
Array ( [id] => 13597781 [patent_doc_number] => 20180350439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING TCAM CELL ARRAYS CAPABLE OF SKIPPING TCAM-CELL SEARCH IN RESPONSE TO CONTROL SIGNAL [patent_app_type] => utility [patent_app_number] => 16/056321 [patent_app_country] => US [patent_app_date] => 2018-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16056321 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/056321
Semiconductor device including TCAM cell arrays capable of skipping TCAM-cell search in response to control signal Aug 5, 2018 Issued
Array ( [id] => 14445847 [patent_doc_number] => 20190180797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => MEMORY SYSTEM FOR ADJUSTING CLOCK FREQUENCY [patent_app_type] => utility [patent_app_number] => 16/054633 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054633 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/054633
Memory system for adjusting clock frequency Aug 2, 2018 Issued
Array ( [id] => 14587263 [patent_doc_number] => 20190221240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => SEMICONDUCTOR PACKAGE WITH CLOCK SHARING AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/053129 [patent_app_country] => US [patent_app_date] => 2018-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16053129 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/053129
Semiconductor package with clock sharing and electronic system including the same Aug 1, 2018 Issued
Array ( [id] => 15732937 [patent_doc_number] => 10614901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Memory controller, information processing system, and nonvolatile-memory defect determination method [patent_app_type] => utility [patent_app_number] => 16/052043 [patent_app_country] => US [patent_app_date] => 2018-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10085 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16052043 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/052043
Memory controller, information processing system, and nonvolatile-memory defect determination method Jul 31, 2018 Issued
Array ( [id] => 15822597 [patent_doc_number] => 10636492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Memory device having plurality of memory cell strings, plurality of source select transistors and plurality of drain select transistors and method of operating a memory device having improved threshold voltage distributions of select transistors [patent_app_type] => utility [patent_app_number] => 16/050913 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9287 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050913 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050913
Memory device having plurality of memory cell strings, plurality of source select transistors and plurality of drain select transistors and method of operating a memory device having improved threshold voltage distributions of select transistors Jul 30, 2018 Issued
Array ( [id] => 15462049 [patent_doc_number] => 20200043849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => POWER TRANSISTOR COUPLED TO MULTIPLE SENSE TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/050383 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050383 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050383
Power transistor coupled to multiple sense transistors Jul 30, 2018 Issued
Array ( [id] => 15611473 [patent_doc_number] => 10586806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Semiconductor memory device with a three-dimensional stacked memory cell structure [patent_app_type] => utility [patent_app_number] => 16/047811 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 4491 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047811 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/047811
Semiconductor memory device with a three-dimensional stacked memory cell structure Jul 26, 2018 Issued
Array ( [id] => 13996261 [patent_doc_number] => 20190067288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => Memory Circuitry [patent_app_type] => utility [patent_app_number] => 16/044887 [patent_app_country] => US [patent_app_date] => 2018-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16044887 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/044887
Memory circuitry having a pair of immediately-adjacent memory arrays having space laterally-there-between that has a conductive interconnect in the space Jul 24, 2018 Issued
Array ( [id] => 15442219 [patent_doc_number] => 20200035293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => EXTENDED WRITE MODES FOR NON-VOLATILE STATIC RANDOM ACCESS MEMORY ARCHITECTURES HAVING WORD LEVEL SWITCHES [patent_app_type] => utility [patent_app_number] => 16/043497 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043497 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/043497
Extended write modes for non-volatile static random access memory architectures having word level switches Jul 23, 2018 Issued
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