Search

Corey S. Faherty

Examiner (ID: 5369, Phone: (571)270-1319 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1281
Issued Applications
1020
Pending Applications
72
Abandoned Applications
208

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20883521 [patent_doc_number] => 12699564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Segment load and stores [patent_app_type] => utility [patent_app_number] => 19/017172 [patent_app_country] => US [patent_app_date] => 2025-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3394 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19017172 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/017172
Segment Load and Stores Jan 9, 2025 Pending
Array ( [id] => 20738274 [patent_doc_number] => 20260147575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-28 [patent_title] => BRANCH PREDICTION USING MULTIPLE TABLES [patent_app_type] => utility [patent_app_number] => 18/958603 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18958603 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/958603
BRANCH PREDICTION USING MULTIPLE TABLES Nov 24, 2024 Pending
Array ( [id] => 20070698 [patent_doc_number] => 20250208920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => CONTEXT AWARE FREQUENCY PRIORITIZATION [patent_app_type] => utility [patent_app_number] => 18/955811 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955811 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/955811
CONTEXT AWARE FREQUENCY PRIORITIZATION Nov 20, 2024 Pending
Array ( [id] => 20380427 [patent_doc_number] => 20250362920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => PROCESSING APPARATUS, METHOD FOR PROCESSING INSTRUCTIONS, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/938844 [patent_app_country] => US [patent_app_date] => 2024-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18938844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/938844
PROCESSING APPARATUS, METHOD FOR PROCESSING INSTRUCTIONS, AND ELECTRONIC DEVICE Nov 5, 2024 Pending
Array ( [id] => 20680362 [patent_doc_number] => 20260119181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => PIPELINE STAGE ALLOCATION [patent_app_type] => utility [patent_app_number] => 18/932968 [patent_app_country] => US [patent_app_date] => 2024-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18932968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/932968
PIPELINE STAGE ALLOCATION Oct 30, 2024 Pending
Array ( [id] => 20680363 [patent_doc_number] => 20260119182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => System and Method for Single Instruction, Multiple Data (SIMD) Enhancements of ARM64 Processors [patent_app_type] => utility [patent_app_number] => 18/930526 [patent_app_country] => US [patent_app_date] => 2024-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18930526 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/930526
System and Method for Single Instruction, Multiple Data (SIMD) Enhancements of ARM64 Processors Oct 28, 2024 Pending
Array ( [id] => 20680353 [patent_doc_number] => 20260119172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => GATHER ACCELERATED ADDRESS SPACE [patent_app_type] => utility [patent_app_number] => 18/926133 [patent_app_country] => US [patent_app_date] => 2024-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926133 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/926133
GATHER ACCELERATED ADDRESS SPACE Oct 23, 2024 Pending
Array ( [id] => 20000604 [patent_doc_number] => 20250138826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => Processor, Instruction Fetching Method, and Computer System [patent_app_type] => utility [patent_app_number] => 18/919793 [patent_app_country] => US [patent_app_date] => 2024-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919793 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/919793
Processor, Instruction Fetching Method, and Computer System Oct 17, 2024 Pending
Array ( [id] => 20061585 [patent_doc_number] => 20250199807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SEMICONDUCTOR DEVICE, DEBUGGING SYSTEM, CONTROL METHOD FOR SEMICONDUCTOR DEVICE, AND DEBUGGING METHOD [patent_app_type] => utility [patent_app_number] => 18/918198 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18918198 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/918198
SEMICONDUCTOR DEVICE, DEBUGGING SYSTEM, CONTROL METHOD FOR SEMICONDUCTOR DEVICE, AND DEBUGGING METHOD Oct 16, 2024 Pending
Array ( [id] => 19694923 [patent_doc_number] => 20250013468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => INSTRUCTION TRANSLATION METHOD AND RELATED DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 18/898309 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11832 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18898309 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/898309
Instruction translation method and related device thereof Sep 25, 2024 Issued
Array ( [id] => 20828158 [patent_doc_number] => 12681725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => Operand selection circuitry [patent_app_type] => utility [patent_app_number] => 18/818134 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18818134 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/818134
Operand selection circuitry Aug 27, 2024 Issued
Array ( [id] => 20828157 [patent_doc_number] => 12681724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => Systems, apparatuses, and methods for chained fused multiply add [patent_app_type] => utility [patent_app_number] => 18/815382 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 16562 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18815382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/815382
Systems, apparatuses, and methods for chained fused multiply add Aug 25, 2024 Issued
Array ( [id] => 20440291 [patent_doc_number] => 12511127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Dynamic reconfiguration of a multi-core processor to a unified core [patent_app_type] => utility [patent_app_number] => 18/813657 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11311 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18813657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/813657
Dynamic reconfiguration of a multi-core processor to a unified core Aug 22, 2024 Issued
Array ( [id] => 20994760 [patent_doc_number] => 12743395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-22 [patent_title] => Dynamic reconfiguration of a unified core processor to a multi-core processor [patent_app_type] => utility [patent_app_number] => 18/813666 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18813666 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/813666
DYNAMIC RECONFIGURATION OF A UNIFIED CORE PROCESSOR TO A MULTI-CORE PROCESSOR Aug 22, 2024 Pending
Array ( [id] => 20052173 [patent_doc_number] => 20250190395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => DYNAMIC PROCESSOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/813501 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18813501 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/813501
DYNAMIC PROCESSOR ARCHITECTURE Aug 22, 2024 Pending
Array ( [id] => 20673190 [patent_doc_number] => 12613702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Processor and compiler for secure multiparty computation [patent_app_type] => utility [patent_app_number] => 18/811392 [patent_app_country] => US [patent_app_date] => 2024-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3675 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18811392 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/811392
Processor and compiler for secure multiparty computation Aug 20, 2024 Issued
Array ( [id] => 20513377 [patent_doc_number] => 20260037478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING DIRECT MEMORY ACCESS DATA TRANSFERS [patent_app_type] => utility [patent_app_number] => 18/790015 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790015 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790015
SYSTEMS AND METHODS FOR PERFORMING DIRECT MEMORY ACCESS DATA TRANSFERS Jul 30, 2024 Pending
Array ( [id] => 20828239 [patent_doc_number] => 12681806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => Method to reset configurable units in a reconfigurable processor [patent_app_type] => utility [patent_app_number] => 18/788391 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 12461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788391 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788391
Method to reset configurable units in a reconfigurable processor Jul 29, 2024 Issued
Array ( [id] => 20500566 [patent_doc_number] => 20260030026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => PREDICTIVELY FETCHING A BRANCH BASED ON A FETCH GROUP ADDRESS AND BRANCH HISTORY EARLY IN AN INSTRUCTION FETCH CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/782772 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18782772 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/782772
PREDICTIVELY FETCHING A BRANCH BASED ON A FETCH GROUP ADDRESS AND BRANCH HISTORY EARLY IN AN INSTRUCTION FETCH CIRCUIT Jul 23, 2024 Pending
Array ( [id] => 20731998 [patent_doc_number] => 12639256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Controllers in data processing engine columns [patent_app_type] => utility [patent_app_number] => 18/781952 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6595 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781952 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781952
Controllers in data processing engine columns Jul 22, 2024 Issued
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