
Corey S. Faherty
Examiner (ID: 5369, Phone: (571)270-1319 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183 |
| Total Applications | 1281 |
| Issued Applications | 1020 |
| Pending Applications | 72 |
| Abandoned Applications | 208 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17069311
[patent_doc_number] => 20210271527
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-02
[patent_title] => Synchronization Amongst Processor Tiles
[patent_app_type] => utility
[patent_app_number] => 17/320904
[patent_app_country] => US
[patent_app_date] => 2021-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25563
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17320904
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/320904 | Synchronization amongst processor tiles | May 13, 2021 | Issued |
Array
(
[id] => 18486878
[patent_doc_number] => 20230214224
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-06
[patent_title] => TECHNIQUE FOR COLLECTING STATE INFORMATION OF AN APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/998299
[patent_app_country] => US
[patent_app_date] => 2021-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13564
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17998299
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/998299 | Technique for collecting state information of an apparatus | May 12, 2021 | Issued |
Array
(
[id] => 20344800
[patent_doc_number] => 12468531
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-11
[patent_title] => Data processing method and apparatus, and related product
[patent_app_type] => utility
[patent_app_number] => 17/619774
[patent_app_country] => US
[patent_app_date] => 2021-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1244
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17619774
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/619774 | Data processing method and apparatus, and related product | Apr 27, 2021 | Issued |
Array
(
[id] => 19250996
[patent_doc_number] => 20240201986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-20
[patent_title] => ACCELERATOR CONTROL SYSTEM, ACCELERATOR CONTROL METHOD AND ACCELERATOR CONTROL PROGRAM
[patent_app_type] => utility
[patent_app_number] => 18/287193
[patent_app_country] => US
[patent_app_date] => 2021-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5198
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18287193
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/287193 | Accelerator control system, accelerator control method and accelerator control program | Apr 21, 2021 | Issued |
Array
(
[id] => 17046674
[patent_doc_number] => 11099854
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-08-24
[patent_title] => Pipelined operations in neural networks
[patent_app_type] => utility
[patent_app_number] => 17/231711
[patent_app_country] => US
[patent_app_date] => 2021-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 15846
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 352
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231711
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/231711 | Pipelined operations in neural networks | Apr 14, 2021 | Issued |
Array
(
[id] => 19732962
[patent_doc_number] => 12210961
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Intelligent processor, data processing method and storage medium
[patent_app_type] => utility
[patent_app_number] => 17/227468
[patent_app_country] => US
[patent_app_date] => 2021-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6392
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227468
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/227468 | Intelligent processor, data processing method and storage medium | Apr 11, 2021 | Issued |
Array
(
[id] => 16979834
[patent_doc_number] => 20210224071
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => PROCESSING PIPELINE WITH FIRST AND SECOND PROCESSING MODES HAVING DIFFERENT PERFORMANCE OR ENERGY CONSUMPTION CHARACTERISTICS
[patent_app_type] => utility
[patent_app_number] => 17/224248
[patent_app_country] => US
[patent_app_date] => 2021-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9631
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224248
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/224248 | Processing pipeline with first and second processing modes having different performance or energy consumption characteristics | Apr 6, 2021 | Issued |
Array
(
[id] => 17915625
[patent_doc_number] => 20220318021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => WAVEFRONT SELECTION AND EXECUTION
[patent_app_type] => utility
[patent_app_number] => 17/219775
[patent_app_country] => US
[patent_app_date] => 2021-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7074
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219775
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/219775 | Wavefront selection and execution | Mar 30, 2021 | Issued |
Array
(
[id] => 17454787
[patent_doc_number] => 11269646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-08
[patent_title] => Instruction scheduling patterns on decoupled systems
[patent_app_type] => utility
[patent_app_number] => 17/215394
[patent_app_country] => US
[patent_app_date] => 2021-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 13630
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215394
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/215394 | Instruction scheduling patterns on decoupled systems | Mar 28, 2021 | Issued |
Array
(
[id] => 18356672
[patent_doc_number] => 11645072
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-09
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/216323
[patent_app_country] => US
[patent_app_date] => 2021-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 11159
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216323
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/216323 | Semiconductor device | Mar 28, 2021 | Issued |
Array
(
[id] => 17786409
[patent_doc_number] => 11409532
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-08-09
[patent_title] => Selecting instructions for a value predictor
[patent_app_type] => utility
[patent_app_number] => 17/215429
[patent_app_country] => US
[patent_app_date] => 2021-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 7027
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215429
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/215429 | Selecting instructions for a value predictor | Mar 28, 2021 | Issued |
Array
(
[id] => 19765027
[patent_doc_number] => 12223318
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-11
[patent_title] => Apparatus and method for managing unsupported instruction set architecture (ISA) features in a virtualized environment
[patent_app_type] => utility
[patent_app_number] => 17/214572
[patent_app_country] => US
[patent_app_date] => 2021-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 32
[patent_no_of_words] => 16974
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214572
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/214572 | Apparatus and method for managing unsupported instruction set architecture (ISA) features in a virtualized environment | Mar 25, 2021 | Issued |
Array
(
[id] => 19107779
[patent_doc_number] => 11960889
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-16
[patent_title] => Method and system for optimizing data transfer from one memory to another memory
[patent_app_type] => utility
[patent_app_number] => 17/914262
[patent_app_country] => US
[patent_app_date] => 2021-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 13218
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17914262
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/914262 | Method and system for optimizing data transfer from one memory to another memory | Mar 24, 2021 | Issued |
Array
(
[id] => 18322226
[patent_doc_number] => 20230120354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-20
[patent_title] => METHOD AND SYSTEM FOR OPTIMIZING DATA TRANSFER FROM ONE MEMORY TO ANOTHER MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/914259
[patent_app_country] => US
[patent_app_date] => 2021-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13356
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17914259
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/914259 | Method and system for optimizing data transfer from one memory to another memory | Mar 24, 2021 | Issued |
Array
(
[id] => 17157822
[patent_doc_number] => 20210318873
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-14
[patent_title] => Circuit for Verifying the Content of Registers
[patent_app_type] => utility
[patent_app_number] => 17/211546
[patent_app_country] => US
[patent_app_date] => 2021-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4908
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211546
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/211546 | Circuit for verifying the content of registers | Mar 23, 2021 | Issued |
Array
(
[id] => 17621847
[patent_doc_number] => 11340903
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-24
[patent_title] => Processing method, device, equipment and storage medium of loop instruction
[patent_app_type] => utility
[patent_app_number] => 17/210046
[patent_app_country] => US
[patent_app_date] => 2021-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 12477
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210046
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/210046 | Processing method, device, equipment and storage medium of loop instruction | Mar 22, 2021 | Issued |
Array
(
[id] => 18015222
[patent_doc_number] => 11507520
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-22
[patent_title] => Tracking streaming engine vector predicates to control processor execution
[patent_app_type] => utility
[patent_app_number] => 17/187984
[patent_app_country] => US
[patent_app_date] => 2021-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 37
[patent_no_of_words] => 29528
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187984
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/187984 | Tracking streaming engine vector predicates to control processor execution | Feb 28, 2021 | Issued |
Array
(
[id] => 18400866
[patent_doc_number] => 11663004
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-30
[patent_title] => Vector convert hexadecimal floating point to scaled decimal instruction
[patent_app_type] => utility
[patent_app_number] => 17/186443
[patent_app_country] => US
[patent_app_date] => 2021-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 21
[patent_no_of_words] => 15953
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17186443
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/186443 | Vector convert hexadecimal floating point to scaled decimal instruction | Feb 25, 2021 | Issued |
Array
(
[id] => 17024112
[patent_doc_number] => 20210247983
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-12
[patent_title] => LOAD BALANCING OF TWO PROCESSORS WHEN EXECUTING DIVERSE-REDUNDANT INSTRUCTION SEQUENCES
[patent_app_type] => utility
[patent_app_number] => 17/172897
[patent_app_country] => US
[patent_app_date] => 2021-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2951
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172897
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/172897 | Load balancing of two processors when executing diverse-redundant instruction sequences | Feb 9, 2021 | Issued |
Array
(
[id] => 16872193
[patent_doc_number] => 20210165660
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-03
[patent_title] => SCHEDULING TASKS IN A MULTI-THREADED PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 17/172864
[patent_app_country] => US
[patent_app_date] => 2021-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9783
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172864
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/172864 | Scheduling tasks in a multi-threaded processor | Feb 9, 2021 | Issued |