Search

Corey S. Faherty

Examiner (ID: 5369, Phone: (571)270-1319 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1281
Issued Applications
1020
Pending Applications
72
Abandoned Applications
208

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17128537 [patent_doc_number] => 20210303306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => INSTRUCTION SEQUENCE MERGING AND SPLITTING FOR OPTIMIZED ACCELERATOR IMPLEMENTATION [patent_app_type] => utility [patent_app_number] => 16/836794 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836794 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836794
Instruction sequence merging and splitting for optimized accelerator implementation Mar 30, 2020 Issued
Array ( [id] => 17128535 [patent_doc_number] => 20210303304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => Shadow Stack ISA Extensions to Support Fast Return and Event Delivery (FRED) Architecture [patent_app_type] => utility [patent_app_number] => 16/833599 [patent_app_country] => US [patent_app_date] => 2020-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833599 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833599
Shadow stack ISA extensions to support fast return and event delivery (FRED) architecture Mar 27, 2020 Issued
Array ( [id] => 17128603 [patent_doc_number] => 20210303372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR HARDWARE-ASSISTED LOCKSTEP OF PROCESSOR CORES [patent_app_type] => utility [patent_app_number] => 16/833454 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833454 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833454
Apparatuses, methods, and systems for hardware-assisted lockstep of processor cores Mar 26, 2020 Issued
Array ( [id] => 17722271 [patent_doc_number] => 20220214993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => ELECTRONIC COMPUTING DEVICE [patent_app_type] => utility [patent_app_number] => 17/604658 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17604658 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/604658
Electronic computing device having improved computing efficiency Mar 24, 2020 Issued
Array ( [id] => 16346157 [patent_doc_number] => 20200310808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => PROCESSOR HAVING MULTIPLE OPERATING MODES [patent_app_type] => utility [patent_app_number] => 16/828528 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7950 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16828528 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/828528
Processor having multiple operating modes Mar 23, 2020 Issued
Array ( [id] => 17786512 [patent_doc_number] => 11409636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Processor including debug unit and debug system [patent_app_type] => utility [patent_app_number] => 16/822524 [patent_app_country] => US [patent_app_date] => 2020-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 11514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16822524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/822524
Processor including debug unit and debug system Mar 17, 2020 Issued
Array ( [id] => 16299745 [patent_doc_number] => 20200285468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => METHOD AND DEVICE FOR FLOATING POINT REPRESENTATION WITH VARIABLE PRECISION [patent_app_type] => utility [patent_app_number] => 16/811641 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16811641 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/811641
Method and device for floating point representation with variable precision Mar 5, 2020 Issued
Array ( [id] => 19107777 [patent_doc_number] => 11960887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Graphics processing unit and central processing unit cooperative variable length data bit packing [patent_app_type] => utility [patent_app_number] => 17/795170 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 19016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17795170 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/795170
Graphics processing unit and central processing unit cooperative variable length data bit packing Mar 2, 2020 Issued
Array ( [id] => 17069271 [patent_doc_number] => 20210271487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => FINISH EXCEPTION HANDLING OF AN INSTRUCTION COMPLETION TABLE [patent_app_type] => utility [patent_app_number] => 16/802679 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802679 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/802679
Finish exception handling of an instruction completion table Feb 26, 2020 Issued
Array ( [id] => 16363135 [patent_doc_number] => 20200319886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => SPATIAL AND TEMPORAL MERGING OF REMOTE ATOMIC OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/799619 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799619 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799619
Spatial and temporal merging of remote atomic operations Feb 23, 2020 Issued
Array ( [id] => 17269160 [patent_doc_number] => 11194585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Multiplier-accumulator circuitry having processing pipelines and methods of operating same [patent_app_type] => utility [patent_app_number] => 16/796111 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 33 [patent_no_of_words] => 13526 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796111 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796111
Multiplier-accumulator circuitry having processing pipelines and methods of operating same Feb 19, 2020 Issued
Array ( [id] => 17802139 [patent_doc_number] => 11416440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Controlling timing in computer processing [patent_app_type] => utility [patent_app_number] => 16/790215 [patent_app_country] => US [patent_app_date] => 2020-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10257 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16790215 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/790215
Controlling timing in computer processing Feb 12, 2020 Issued
Array ( [id] => 16178989 [patent_doc_number] => 20200225957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SLICE-BASED ALLOCATION HISTORY BUFFER [patent_app_type] => utility [patent_app_number] => 16/776758 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16776758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/776758
Slice-based allocation history buffer Jan 29, 2020 Issued
Array ( [id] => 16787970 [patent_doc_number] => 10990403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-27 [patent_title] => Predicting an outcome of an instruction following a flush [patent_app_type] => utility [patent_app_number] => 16/752995 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/752995
Predicting an outcome of an instruction following a flush Jan 26, 2020 Issued
Array ( [id] => 16818632 [patent_doc_number] => 11003458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware [patent_app_type] => utility [patent_app_number] => 16/752750 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 11044 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752750 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/752750
Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware Jan 26, 2020 Issued
Array ( [id] => 16979832 [patent_doc_number] => 20210224069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => CALCULATION METHOD AND RELATED PRODUCT [patent_app_type] => utility [patent_app_number] => 16/745743 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 62108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745743 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/745743
Calculation method and related product Jan 16, 2020 Issued
Array ( [id] => 17636781 [patent_doc_number] => 11347505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Processor performance monitor that logs reasons for reservation loss [patent_app_type] => utility [patent_app_number] => 16/743628 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6373 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743628
Processor performance monitor that logs reasons for reservation loss Jan 14, 2020 Issued
Array ( [id] => 15902899 [patent_doc_number] => 20200150969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => COALESCING GLOBAL COMPLETION TABLE ENTRIES IN AN OUT-OF-ORDER PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/738360 [patent_app_country] => US [patent_app_date] => 2020-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16738360 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/738360
Coalescing global completion table entries in an out-of-order processor Jan 8, 2020 Issued
Array ( [id] => 17288217 [patent_doc_number] => 11204767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Context switching locations for compiler-assisted context switching [patent_app_type] => utility [patent_app_number] => 16/734739 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 48 [patent_no_of_words] => 38118 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16734739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/734739
Context switching locations for compiler-assisted context switching Jan 5, 2020 Issued
Array ( [id] => 16240293 [patent_doc_number] => 20200257527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECISION INPUT OPERANDS [patent_app_type] => utility [patent_app_number] => 16/735381 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/735381
Instructions for fused multiply-add operations with variable precision input operands Jan 5, 2020 Issued
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