Search

Corey S. Faherty

Examiner (ID: 5369, Phone: (571)270-1319 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1281
Issued Applications
1020
Pending Applications
72
Abandoned Applications
208

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17288219 [patent_doc_number] => 11204769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines [patent_app_type] => utility [patent_app_number] => 16/733193 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10804 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16733193 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/733193
Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines Jan 1, 2020 Issued
Array ( [id] => 17121067 [patent_doc_number] => 11132201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => System, apparatus and method for dynamic pipeline stage control of data path dominant circuitry of an integrated circuit [patent_app_type] => utility [patent_app_number] => 16/725041 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 10473 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16725041 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/725041
System, apparatus and method for dynamic pipeline stage control of data path dominant circuitry of an integrated circuit Dec 22, 2019 Issued
Array ( [id] => 17492167 [patent_doc_number] => 11281470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Argmax use for machine learning [patent_app_type] => utility [patent_app_number] => 16/721833 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721833 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721833
Argmax use for machine learning Dec 18, 2019 Issued
Array ( [id] => 15935795 [patent_doc_number] => 20200159531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => COMPUTING DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/714915 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714915 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714915
Computing device and method Dec 15, 2019 Issued
Array ( [id] => 18506311 [patent_doc_number] => 11704125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Computing device and method [patent_app_type] => utility [patent_app_number] => 16/715301 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 27703 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715301 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715301
Computing device and method Dec 15, 2019 Issued
Array ( [id] => 18519781 [patent_doc_number] => 11709672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Computing device and method [patent_app_type] => utility [patent_app_number] => 16/715170 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 27693 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715170 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715170
Computing device and method Dec 15, 2019 Issued
Array ( [id] => 17180037 [patent_doc_number] => 11157279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Performance scaling for binary translation [patent_app_type] => utility [patent_app_number] => 16/714626 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714626 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714626
Performance scaling for binary translation Dec 12, 2019 Issued
Array ( [id] => 16903156 [patent_doc_number] => 20210182072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => MARKER-BASED PROCESSOR INSTRUCTION GROUPING [patent_app_type] => utility [patent_app_number] => 16/713432 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713432 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713432
Marker-based processor instruction grouping Dec 12, 2019 Issued
Array ( [id] => 16794765 [patent_doc_number] => 20210124582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => TECHNIQUES FOR EFFICIENTLY TRANSFERRING DATA TO A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/712083 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16712083 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/712083
Techniques for efficiently transferring data to a processor Dec 11, 2019 Issued
Array ( [id] => 16894953 [patent_doc_number] => 11036506 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-15 [patent_title] => Memory systems and methods for handling vector data [patent_app_type] => utility [patent_app_number] => 16/710862 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 23256 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710862 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/710862
Memory systems and methods for handling vector data Dec 10, 2019 Issued
Array ( [id] => 18262060 [patent_doc_number] => 11609761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Inline data inspection for workload simplification [patent_app_type] => utility [patent_app_number] => 16/708261 [patent_app_country] => US [patent_app_date] => 2019-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9382 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16708261 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/708261
Inline data inspection for workload simplification Dec 8, 2019 Issued
Array ( [id] => 16095283 [patent_doc_number] => 20200201628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => EFFICIENT IMPLEMENTATION OF COMPLEX VECTOR FUSED MULTIPLY ADD AND COMPLEX VECTOR MULTIPLY [patent_app_type] => utility [patent_app_number] => 16/701082 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16701082 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/701082
Efficient implementation of complex vector fused multiply add and complex vector multiply Dec 1, 2019 Issued
Array ( [id] => 15561683 [patent_doc_number] => 20200065253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => DETERMINING THE EFFECTIVENESS OF PREFETCH INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/668527 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16668527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/668527
Determining the effectiveness of prefetch instructions Oct 29, 2019 Issued
Array ( [id] => 16764458 [patent_doc_number] => 20210110040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => PROTECTING AGAINST OUT-OF-BOUNDS BUFFER REFERENCES [patent_app_type] => utility [patent_app_number] => 16/601633 [patent_app_country] => US [patent_app_date] => 2019-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601633 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/601633
Protecting against out-of-bounds buffer references Oct 14, 2019 Issued
Array ( [id] => 17572829 [patent_doc_number] => 11321097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Super-thread processor [patent_app_type] => utility [patent_app_number] => 16/596417 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8071 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596417 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/596417
Super-thread processor Oct 7, 2019 Issued
Array ( [id] => 17786406 [patent_doc_number] => 11409529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => RISC-V implemented processor with hardware acceleration supporting user defined instruction set and method thereof [patent_app_type] => utility [patent_app_number] => 17/041384 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7657 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17041384 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/041384
RISC-V implemented processor with hardware acceleration supporting user defined instruction set and method thereof Oct 3, 2019 Issued
Array ( [id] => 17325265 [patent_doc_number] => 11216277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Apparatus and method of capturing a register state [patent_app_type] => utility [patent_app_number] => 16/583729 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583729 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583729
Apparatus and method of capturing a register state Sep 25, 2019 Issued
Array ( [id] => 15350071 [patent_doc_number] => 20200012927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => COMPUTING DEVICE, A SYSTEM AND A METHOD FOR PARALLEL PROCESSING OF DATA STREAMS [patent_app_type] => utility [patent_app_number] => 16/571416 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/571416
Computing device, a system and a method for parallel processing of data streams Sep 15, 2019 Issued
Array ( [id] => 17846642 [patent_doc_number] => 11436015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Look-up table read [patent_app_type] => utility [patent_app_number] => 16/570874 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 40 [patent_no_of_words] => 23497 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570874 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/570874
Look-up table read Sep 12, 2019 Issued
Array ( [id] => 15594265 [patent_doc_number] => 20200073667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => ELECTRONIC DEVICE AND METHOD FOR DATA PROCESSING USING VIRTUAL REGISTER MODE [patent_app_type] => utility [patent_app_number] => 16/564652 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564652 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/564652
Electronic device and method for data processing using virtual register mode Sep 8, 2019 Issued
Menu