Search

Corey S. Faherty

Examiner (ID: 5369, Phone: (571)270-1319 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1281
Issued Applications
1020
Pending Applications
72
Abandoned Applications
208

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15297351 [patent_doc_number] => 20190391811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => MULTI-VARIATE STRIDED READ OPERATIONS FOR ACCESSING MATRIX OPERANDS [patent_app_type] => utility [patent_app_number] => 16/556223 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556223 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/556223
Multi-variate strided read operations for accessing matrix operands Aug 28, 2019 Issued
Array ( [id] => 16659292 [patent_doc_number] => 20210055929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => Register File Arbitration [patent_app_type] => utility [patent_app_number] => 16/548797 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548797 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548797
Register file arbitration Aug 21, 2019 Issued
Array ( [id] => 17308991 [patent_doc_number] => 11210101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Arithmetic processing device and control method implemented by arithmetic processing device [patent_app_type] => utility [patent_app_number] => 16/547653 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 21341 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547653
Arithmetic processing device and control method implemented by arithmetic processing device Aug 21, 2019 Issued
Array ( [id] => 17515523 [patent_doc_number] => 11294672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Routing circuitry for permutation of single-instruction multiple-data operands [patent_app_type] => utility [patent_app_number] => 16/548812 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548812 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548812
Routing circuitry for permutation of single-instruction multiple-data operands Aug 21, 2019 Issued
Array ( [id] => 16478303 [patent_doc_number] => 10853251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Diadic memory operations and expanded memory frontend operations [patent_app_type] => utility [patent_app_number] => 16/546713 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1800 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546713
Diadic memory operations and expanded memory frontend operations Aug 20, 2019 Issued
Array ( [id] => 15500533 [patent_doc_number] => 20200050455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => COMMAND INTERPRETER OR COMMAND PARSER BASED CONTROL ARCHITECTURE FOR AIRCRAFT CONTROL, INTERFACE UNITS AND/OR ILLUMINATED PUSHBUTTON SWITCHES [patent_app_type] => utility [patent_app_number] => 16/539640 [patent_app_country] => US [patent_app_date] => 2019-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16539640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/539640
Command interpreter or command parser based control architecture for aircraft control, interface units and/or illuminated pushbutton switches Aug 12, 2019 Issued
Array ( [id] => 15182223 [patent_doc_number] => 20190361703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => METHOD AND APPARATUS FOR RENAMING SOURCE OPERANDS OF INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/537633 [patent_app_country] => US [patent_app_date] => 2019-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537633 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537633
METHOD AND APPARATUS FOR RENAMING SOURCE OPERANDS OF INSTRUCTIONS Aug 11, 2019 Abandoned
Array ( [id] => 16879805 [patent_doc_number] => 11029952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Hardware apparatuses and methods to switch shadow stack pointers [patent_app_type] => utility [patent_app_number] => 16/534970 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 15371 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534970 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534970
Hardware apparatuses and methods to switch shadow stack pointers Aug 6, 2019 Issued
Array ( [id] => 15120927 [patent_doc_number] => 20190347096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/520761 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16520761 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/520761
Semiconductor device Jul 23, 2019 Issued
Array ( [id] => 15501463 [patent_doc_number] => 20200050920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => TECHNIQUES FOR EFFICIENTLY OPERATING A PROCESSING SYSTEM BASED ON ENERGY CHARACTERISTICS OF INSTRUCTIONS AND MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 16/514078 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514078
Techniques for efficiently operating a processing system based on energy characteristics of instructions and machine learning Jul 16, 2019 Issued
Array ( [id] => 17437677 [patent_doc_number] => 11263010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Bit string lookup data structure [patent_app_type] => utility [patent_app_number] => 16/506453 [patent_app_country] => US [patent_app_date] => 2019-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 20824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16506453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/506453
Bit string lookup data structure Jul 8, 2019 Issued
Array ( [id] => 16667065 [patent_doc_number] => 10936311 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => Sparse matrix processing circuitry [patent_app_type] => utility [patent_app_number] => 16/505987 [patent_app_country] => US [patent_app_date] => 2019-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 7922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505987 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/505987
Sparse matrix processing circuitry Jul 8, 2019 Issued
Array ( [id] => 15500537 [patent_doc_number] => 20200050457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => METHOD AND APPARATUS FOR EXECUTING INSTRUCTION FOR ARTIFICIAL INTELLIGENCE CHIP [patent_app_type] => utility [patent_app_number] => 16/505913 [patent_app_country] => US [patent_app_date] => 2019-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505913 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/505913
Method and apparatus for executing instruction for artificial intelligence chip Jul 8, 2019 Issued
Array ( [id] => 16494284 [patent_doc_number] => 10860326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Multi-threaded instruction buffer design [patent_app_type] => utility [patent_app_number] => 16/505314 [patent_app_country] => US [patent_app_date] => 2019-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 10492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505314 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/505314
Multi-threaded instruction buffer design Jul 7, 2019 Issued
Array ( [id] => 16494283 [patent_doc_number] => 10860325 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-08 [patent_title] => Dynamic control of processor instruction sets [patent_app_type] => utility [patent_app_number] => 16/503828 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 44 [patent_no_of_words] => 28922 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503828 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503828
Dynamic control of processor instruction sets Jul 4, 2019 Issued
Array ( [id] => 17394765 [patent_doc_number] => 11243779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => System and method for managing execution of processes on a cluster of processing devices [patent_app_type] => utility [patent_app_number] => 16/457741 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3136 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457741 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/457741
System and method for managing execution of processes on a cluster of processing devices Jun 27, 2019 Issued
Array ( [id] => 17238290 [patent_doc_number] => 11182170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => MIMD processor emulated on SIMD architecture [patent_app_type] => utility [patent_app_number] => 15/734729 [patent_app_country] => US [patent_app_date] => 2019-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3938 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15734729 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/734729
MIMD processor emulated on SIMD architecture Jun 5, 2019 Issued
Array ( [id] => 17009318 [patent_doc_number] => 20210240479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => BRANCH PREDICTION CACHE FOR MULTIPLE SOFTWARE WORKLOADS [patent_app_type] => utility [patent_app_number] => 17/052655 [patent_app_country] => US [patent_app_date] => 2019-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17052655 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/052655
Branch prediction cache for multiple software workloads May 8, 2019 Issued
Array ( [id] => 16439197 [patent_doc_number] => 20200356523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => CONTROL FLOW BARRIER AND RECONFIGURABLE DATA PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/407675 [patent_app_country] => US [patent_app_date] => 2019-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16407675 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/407675
Control flow barrier and reconfigurable data processor May 8, 2019 Issued
Array ( [id] => 14719709 [patent_doc_number] => 20190250918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => THREAD TRANSITION MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/397367 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397367 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397367
Thread transition management Apr 28, 2019 Issued
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