Search

Corey S. Faherty

Examiner (ID: 5369, Phone: (571)270-1319 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1281
Issued Applications
1020
Pending Applications
72
Abandoned Applications
208

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16400913 [patent_doc_number] => 20200341771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => RESOLVING OPERAND STORE COMPARE CONFLICTS [patent_app_type] => utility [patent_app_number] => 16/394056 [patent_app_country] => US [patent_app_date] => 2019-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16394056 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/394056
Resolving operand store compare conflicts Apr 24, 2019 Issued
Array ( [id] => 14719713 [patent_doc_number] => 20190250920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => PARSING-ENHANCEMENT FACILITY [patent_app_type] => utility [patent_app_number] => 16/394025 [patent_app_country] => US [patent_app_date] => 2019-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4915 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16394025 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/394025
Parsing-enhancement facility Apr 24, 2019 Issued
Array ( [id] => 17209438 [patent_doc_number] => 11169810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Micro-operation cache using predictive allocation [patent_app_type] => utility [patent_app_number] => 16/374743 [patent_app_country] => US [patent_app_date] => 2019-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7435 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16374743 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/374743
Micro-operation cache using predictive allocation Apr 2, 2019 Issued
Array ( [id] => 16363137 [patent_doc_number] => 20200319888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => WIDENING MEMORY ACCESS TO AN ALIGNED ADDRESS FOR UNALIGNED MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/374509 [patent_app_country] => US [patent_app_date] => 2019-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16374509 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/374509
Widening memory access to an aligned address for unaligned memory operations Apr 2, 2019 Issued
Array ( [id] => 17194963 [patent_doc_number] => 11163720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Apparatus and method for processing an instruction matrix specifying parallel and dependent operations [patent_app_type] => utility [patent_app_number] => 16/371831 [patent_app_country] => US [patent_app_date] => 2019-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 9232 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371831 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/371831
Apparatus and method for processing an instruction matrix specifying parallel and dependent operations Mar 31, 2019 Issued
Array ( [id] => 14935417 [patent_doc_number] => 20190303346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => Loop Thread Order Execution Control of a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric [patent_app_type] => utility [patent_app_number] => 16/371056 [patent_app_country] => US [patent_app_date] => 2019-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371056 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/371056
Loop thread order execution control of a multi-threaded, self-scheduling reconfigurable computing fabric Mar 30, 2019 Issued
Array ( [id] => 17209584 [patent_doc_number] => 11169957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Systems and methods for reconfigurable systolic arrays [patent_app_type] => utility [patent_app_number] => 16/371017 [patent_app_country] => US [patent_app_date] => 2019-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371017 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/371017
Systems and methods for reconfigurable systolic arrays Mar 30, 2019 Issued
Array ( [id] => 17091579 [patent_doc_number] => 11119768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Conditional branching control for a multi-threaded, self-scheduling reconfigurable computing fabric [patent_app_type] => utility [patent_app_number] => 16/371060 [patent_app_country] => US [patent_app_date] => 2019-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 29 [patent_no_of_words] => 31692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371060 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/371060
Conditional branching control for a multi-threaded, self-scheduling reconfigurable computing fabric Mar 30, 2019 Issued
Array ( [id] => 14935055 [patent_doc_number] => 20190303165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => Loop Execution Control for a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric Using a Reenter Queue [patent_app_type] => utility [patent_app_number] => 16/371065 [patent_app_country] => US [patent_app_date] => 2019-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371065 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/371065
Loop execution control for a multi-threaded, self-scheduling reconfigurable computing fabric using a reenter queue Mar 30, 2019 Issued
Array ( [id] => 16346153 [patent_doc_number] => 20200310804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => METHOD AND APPARATUS FOR VECTOR-MATRIX COMPARISON [patent_app_type] => utility [patent_app_number] => 16/370922 [patent_app_country] => US [patent_app_date] => 2019-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370922
Method and apparatus for vector-matrix comparison Mar 29, 2019 Issued
Array ( [id] => 16346153 [patent_doc_number] => 20200310804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => METHOD AND APPARATUS FOR VECTOR-MATRIX COMPARISON [patent_app_type] => utility [patent_app_number] => 16/370922 [patent_app_country] => US [patent_app_date] => 2019-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370922
Method and apparatus for vector-matrix comparison Mar 29, 2019 Issued
Array ( [id] => 16346153 [patent_doc_number] => 20200310804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => METHOD AND APPARATUS FOR VECTOR-MATRIX COMPARISON [patent_app_type] => utility [patent_app_number] => 16/370922 [patent_app_country] => US [patent_app_date] => 2019-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370922
Method and apparatus for vector-matrix comparison Mar 29, 2019 Issued
Array ( [id] => 16346153 [patent_doc_number] => 20200310804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => METHOD AND APPARATUS FOR VECTOR-MATRIX COMPARISON [patent_app_type] => utility [patent_app_number] => 16/370922 [patent_app_country] => US [patent_app_date] => 2019-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370922
Method and apparatus for vector-matrix comparison Mar 29, 2019 Issued
Array ( [id] => 16346163 [patent_doc_number] => 20200310814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => REDUCTION OF DATA CACHE ACCESS IN A PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/368536 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6681 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368536 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/368536
Reduction of data cache access in a processing system Mar 27, 2019 Issued
Array ( [id] => 16346147 [patent_doc_number] => 20200310798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => Technology For Providing Memory Atomicity With Low Overhead [patent_app_type] => utility [patent_app_number] => 16/367409 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16367409 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/367409
Technology For Providing Memory Atomicity With Low Overhead Mar 27, 2019 Abandoned
Array ( [id] => 14585349 [patent_doc_number] => 20190220283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => LOAD/STORE UNIT FOR A PROCESSOR, AND APPLICATIONS THEREOF [patent_app_type] => utility [patent_app_number] => 16/366328 [patent_app_country] => US [patent_app_date] => 2019-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16366328 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/366328
Load/store unit for a processor, and applications thereof Mar 26, 2019 Issued
Array ( [id] => 16240300 [patent_doc_number] => 20200257534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => HIERARCHICAL METADATA PREDICTOR WITH PERIODIC UPDATES [patent_app_type] => utility [patent_app_number] => 16/274710 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16274710 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/274710
Hierarchical metadata predictor with periodic updates Feb 12, 2019 Issued
Array ( [id] => 14411229 [patent_doc_number] => 20190171458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => PERFORMANCE SCALING FOR BINARY TRANSLATION [patent_app_type] => utility [patent_app_number] => 16/273080 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16273080 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/273080
Performance scaling for binary translation Feb 10, 2019 Issued
Array ( [id] => 16279004 [patent_doc_number] => 10762035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-01 [patent_title] => Matrix tiling to accelerate computing in redundant matrices [patent_app_type] => utility [patent_app_number] => 16/271638 [patent_app_country] => US [patent_app_date] => 2019-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16271638 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/271638
Matrix tiling to accelerate computing in redundant matrices Feb 7, 2019 Issued
Array ( [id] => 16217158 [patent_doc_number] => 10732970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset [patent_app_type] => utility [patent_app_number] => 16/271675 [patent_app_country] => US [patent_app_date] => 2019-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 41 [patent_no_of_words] => 27315 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16271675 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/271675
Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset Feb 7, 2019 Issued
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