
Corey S. Faherty
Examiner (ID: 5369, Phone: (571)270-1319 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183 |
| Total Applications | 1281 |
| Issued Applications | 1020 |
| Pending Applications | 72 |
| Abandoned Applications | 208 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15996401
[patent_doc_number] => 20200174071
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => DEBUG COMMAND EXECUTION USING EXISTING DATAPATH CIRCUITRY
[patent_app_type] => utility
[patent_app_number] => 16/264039
[patent_app_country] => US
[patent_app_date] => 2019-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6259
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16264039
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/264039 | Debug command execution using existing datapath circuitry | Jan 30, 2019 | Issued |
Array
(
[id] => 16232550
[patent_doc_number] => 10740100
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-11
[patent_title] => Deinterleave strided data elements processors, methods, systems, and instructions
[patent_app_type] => utility
[patent_app_number] => 16/260121
[patent_app_country] => US
[patent_app_date] => 2019-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 32
[patent_no_of_words] => 33657
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16260121
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/260121 | Deinterleave strided data elements processors, methods, systems, and instructions | Jan 28, 2019 | Issued |
Array
(
[id] => 16651968
[patent_doc_number] => 10929145
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-23
[patent_title] => Mask generation using reduction operators and scatter use thereof
[patent_app_type] => utility
[patent_app_number] => 16/235940
[patent_app_country] => US
[patent_app_date] => 2018-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 27
[patent_no_of_words] => 13393
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16235940
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/235940 | Mask generation using reduction operators and scatter use thereof | Dec 27, 2018 | Issued |
Array
(
[id] => 16116345
[patent_doc_number] => 20200210195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => Managing Trace Information Storage Using Pipeline Instruction Insertion and Filtering
[patent_app_type] => utility
[patent_app_number] => 16/234813
[patent_app_country] => US
[patent_app_date] => 2018-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4237
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234813
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/234813 | Managing trace information storage using pipeline instruction insertion and filtering | Dec 27, 2018 | Issued |
Array
(
[id] => 17001419
[patent_doc_number] => 11080230
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-03
[patent_title] => Hardware accelerators and methods for out-of-order processing
[patent_app_type] => utility
[patent_app_number] => 16/236154
[patent_app_country] => US
[patent_app_date] => 2018-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 27
[patent_no_of_words] => 20872
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236154
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/236154 | Hardware accelerators and methods for out-of-order processing | Dec 27, 2018 | Issued |
Array
(
[id] => 16116313
[patent_doc_number] => 20200210179
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => UNIFORMITY CHECK BASED INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 16/235908
[patent_app_country] => US
[patent_app_date] => 2018-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13551
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16235908
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/235908 | UNIFORMITY CHECK BASED INSTRUCTIONS | Dec 27, 2018 | Abandoned |
Array
(
[id] => 18430375
[patent_doc_number] => 11675594
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks
[patent_app_type] => utility
[patent_app_number] => 16/236049
[patent_app_country] => US
[patent_app_date] => 2018-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 27
[patent_no_of_words] => 13607
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236049
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/236049 | Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks | Dec 27, 2018 | Issued |
Array
(
[id] => 14585343
[patent_doc_number] => 20190220280
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-18
[patent_title] => PROCESSOR TO EXECUTE SHIFT RIGHT MERGE INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 16/208534
[patent_app_country] => US
[patent_app_date] => 2018-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13812
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 281
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208534
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/208534 | Processor to execute shift right merge instructions | Dec 2, 2018 | Issued |
Array
(
[id] => 15997753
[patent_doc_number] => 20200174747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => Reformatting Matrices to Improve Computing Efficiency
[patent_app_type] => utility
[patent_app_number] => 16/205208
[patent_app_country] => US
[patent_app_date] => 2018-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8462
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205208
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/205208 | Reformatting matrices to improve computing efficiency | Nov 28, 2018 | Issued |
Array
(
[id] => 16314579
[patent_doc_number] => 20200293317
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-17
[patent_title] => DATA PROCESSING DEVICE DATA PROCESSING METHOD AND RECORDING MEDIUM
[patent_app_type] => utility
[patent_app_number] => 16/762317
[patent_app_country] => US
[patent_app_date] => 2018-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8576
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16762317
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/762317 | Data processing device data processing method and recording medium | Nov 8, 2018 | Issued |
Array
(
[id] => 14314841
[patent_doc_number] => 20190147124
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-16
[patent_title] => OPERATION MODEL GENERATOR AND OPERATION MODEL GENERATION METHOD
[patent_app_type] => utility
[patent_app_number] => 16/182653
[patent_app_country] => US
[patent_app_date] => 2018-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11798
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16182653
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/182653 | OPERATION MODEL GENERATOR AND OPERATION MODEL GENERATION METHOD | Nov 6, 2018 | Abandoned |
Array
(
[id] => 15654039
[patent_doc_number] => 20200089550
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-19
[patent_title] => BROADCAST COMMAND AND RESPONSE
[patent_app_type] => utility
[patent_app_number] => 16/171451
[patent_app_country] => US
[patent_app_date] => 2018-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3412
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171451
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/171451 | Broadcast command and response | Oct 25, 2018 | Issued |
Array
(
[id] => 14218505
[patent_doc_number] => 20190121637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-25
[patent_title] => SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD
[patent_app_type] => utility
[patent_app_number] => 16/169456
[patent_app_country] => US
[patent_app_date] => 2018-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21736
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169456
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/169456 | Systems, apparatuses, and methods for chained fused multiply add | Oct 23, 2018 | Issued |
Array
(
[id] => 15700931
[patent_doc_number] => 10606641
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-31
[patent_title] => Scheduling tasks in a multi-threaded processor
[patent_app_type] => utility
[patent_app_number] => 16/166000
[patent_app_country] => US
[patent_app_date] => 2018-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 10372
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16166000
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/166000 | Scheduling tasks in a multi-threaded processor | Oct 18, 2018 | Issued |
Array
(
[id] => 13907533
[patent_doc_number] => 20190042971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-07
[patent_title] => APPARATUS AND METHOD FOR SCALABLE QUBIT ADDRESSING
[patent_app_type] => utility
[patent_app_number] => 16/144887
[patent_app_country] => US
[patent_app_date] => 2018-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12724
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -30
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16144887
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/144887 | Apparatus and method for scalable qubit addressing | Sep 26, 2018 | Issued |
Array
(
[id] => 14135639
[patent_doc_number] => 20190102209
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-04
[patent_title] => MULTITENANT HOSTED VIRTUAL MACHINE INFRASTRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/128251
[patent_app_country] => US
[patent_app_date] => 2018-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18377
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -52
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16128251
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/128251 | Multitenant hosted virtual machine infrastructure | Sep 10, 2018 | Issued |
Array
(
[id] => 14047329
[patent_doc_number] => 20190079771
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-14
[patent_title] => LOOKAHEAD OUT-OF-ORDER INSTRUCTION FETCH APPARATUS FOR MICROPROCESSORS
[patent_app_type] => utility
[patent_app_number] => 16/125756
[patent_app_country] => US
[patent_app_date] => 2018-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10309
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 366
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16125756
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/125756 | LOOKAHEAD OUT-OF-ORDER INSTRUCTION FETCH APPARATUS FOR MICROPROCESSORS | Sep 8, 2018 | Abandoned |
Array
(
[id] => 17317600
[patent_doc_number] => 20210406649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => COMPUTING DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 16/614215
[patent_app_country] => US
[patent_app_date] => 2018-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 30563
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16614215
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/614215 | Computing device and method | Sep 2, 2018 | Issued |
Array
(
[id] => 15561381
[patent_doc_number] => 20200065102
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-27
[patent_title] => COMPLETION MECHANISM FOR A MICROPROCESSOR INSTRUCTION COMPLETION TABLE
[patent_app_type] => utility
[patent_app_number] => 16/109952
[patent_app_country] => US
[patent_app_date] => 2018-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5777
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16109952
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/109952 | Completion mechanism for a microprocessor instruction completion table | Aug 22, 2018 | Issued |
Array
(
[id] => 16171490
[patent_doc_number] => 10713057
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-14
[patent_title] => Mechanism to stop completions using stop codes in an instruction completion table
[patent_app_type] => utility
[patent_app_number] => 16/110178
[patent_app_country] => US
[patent_app_date] => 2018-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5190
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16110178
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/110178 | Mechanism to stop completions using stop codes in an instruction completion table | Aug 22, 2018 | Issued |