Search

Corey S. Faherty

Examiner (ID: 5369, Phone: (571)270-1319 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1281
Issued Applications
1020
Pending Applications
72
Abandoned Applications
208

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17408883 [patent_doc_number] => 11249765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Performance for GPU exceptions [patent_app_type] => utility [patent_app_number] => 16/109567 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5893 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16109567 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/109567
Performance for GPU exceptions Aug 21, 2018 Issued
Array ( [id] => 16217327 [patent_doc_number] => 10733141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Distributed processor system [patent_app_type] => utility [patent_app_number] => 16/103711 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10498 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103711 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103711
Distributed processor system Aug 13, 2018 Issued
Array ( [id] => 14330641 [patent_doc_number] => 10296339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Thread transition management [patent_app_type] => utility [patent_app_number] => 16/101431 [patent_app_country] => US [patent_app_date] => 2018-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6644 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16101431 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/101431
Thread transition management Aug 10, 2018 Issued
Array ( [id] => 15458993 [patent_doc_number] => 20200042321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => LOW POWER BACK-TO-BACK WAKE UP AND ISSUE FOR PAIRED ISSUE QUEUE IN A MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 16/051380 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/051380
LOW POWER BACK-TO-BACK WAKE UP AND ISSUE FOR PAIRED ISSUE QUEUE IN A MICROPROCESSOR Jul 30, 2018 Abandoned
Array ( [id] => 15788879 [patent_doc_number] => 10628164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-21 [patent_title] => Branch resolve pointer optimization [patent_app_type] => utility [patent_app_number] => 16/048721 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048721 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/048721
Branch resolve pointer optimization Jul 29, 2018 Issued
Array ( [id] => 18803338 [patent_doc_number] => 11836497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Operation module and method thereof [patent_app_type] => utility [patent_app_number] => 16/075836 [patent_app_country] => US [patent_app_date] => 2018-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 23330 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16075836 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/075836
Operation module and method thereof Jul 22, 2018 Issued
Array ( [id] => 16171487 [patent_doc_number] => 10713054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Multiple-table branch target buffer [patent_app_type] => utility [patent_app_number] => 16/030031 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 11959 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030031 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030031
Multiple-table branch target buffer Jul 8, 2018 Issued
Array ( [id] => 13992099 [patent_doc_number] => 20190065207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/026733 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026733 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/026733
Configurable pipeline based on error detection mode in a data processing system Jul 2, 2018 Issued
Array ( [id] => 17091595 [patent_doc_number] => 11119784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Efficient mitigation of side-channel based attacks against speculative execution processing architectures [patent_app_type] => utility [patent_app_number] => 16/023564 [patent_app_country] => US [patent_app_date] => 2018-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 10980 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16023564 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/023564
Efficient mitigation of side-channel based attacks against speculative execution processing architectures Jun 28, 2018 Issued
Array ( [id] => 16446801 [patent_doc_number] => 10838730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Saving and restoring branch prediction state [patent_app_type] => utility [patent_app_number] => 16/018419 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 18128 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16018419 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/018419
Saving and restoring branch prediction state Jun 25, 2018 Issued
Array ( [id] => 15870907 [patent_doc_number] => 20200142857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => HIGH THROUGHPUT PROCESSORS [patent_app_type] => utility [patent_app_number] => 16/625220 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16625220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/625220
High throughput processors Jun 21, 2018 Issued
Array ( [id] => 15919411 [patent_doc_number] => 10656944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Hardware apparatus and methods to prefetch a multidimensional block of elements from a multidimensional array [patent_app_type] => utility [patent_app_number] => 16/004081 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 21382 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004081 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/004081
Hardware apparatus and methods to prefetch a multidimensional block of elements from a multidimensional array Jun 7, 2018 Issued
Array ( [id] => 14282041 [patent_doc_number] => 20190138305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => HARDWARE APPARATUSES AND METHODS RELATING TO ELEMENTAL REGISTER ACCESSES [patent_app_type] => utility [patent_app_number] => 16/003555 [patent_app_country] => US [patent_app_date] => 2018-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16003555 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/003555
Hardware apparatuses and methods relating to elemental register accesses Jun 7, 2018 Issued
Array ( [id] => 15214615 [patent_doc_number] => 20190369994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => PROVIDING MULTI-ELEMENT MULTI-VECTOR (MEMV) REGISTER FILE ACCESS IN VECTOR-PROCESSOR-BASED DEVICES [patent_app_type] => utility [patent_app_number] => 16/000580 [patent_app_country] => US [patent_app_date] => 2018-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000580 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/000580
Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices Jun 4, 2018 Issued
Array ( [id] => 13738145 [patent_doc_number] => 20180373541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => SYSTEM AND METHOD FOR NON-SPECULATIVE REORDERING OF LOAD ACCESSES [patent_app_type] => utility [patent_app_number] => 15/987186 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987186 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987186
System and method for non-speculative reordering of load accesses May 22, 2018 Issued
Array ( [id] => 13432519 [patent_doc_number] => 20180267802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => PARSING-ENHANCEMENT FACILITY [patent_app_type] => utility [patent_app_number] => 15/985274 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15985274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/985274
Parsing-enhancement facility May 20, 2018 Issued
Array ( [id] => 17187215 [patent_doc_number] => 20210334100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => SECURE COMPUTATION DEVICE, COMPARISON METHOD, COMPARISON PROGRAM RECORDING MEDIUM, AND SECURE COMPUTATION SYSTEM [patent_app_type] => utility [patent_app_number] => 16/613967 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16613967 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/613967
Secure computation device, comparison method, comparison program recording medium, and secure computation system May 7, 2018 Issued
Array ( [id] => 15544945 [patent_doc_number] => 10572253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => System and method for reducing non-linearity in mixed signal processing using complex polynomial vector processor [patent_app_type] => utility [patent_app_number] => 15/969356 [patent_app_country] => US [patent_app_date] => 2018-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3745 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 449 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969356 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/969356
System and method for reducing non-linearity in mixed signal processing using complex polynomial vector processor May 1, 2018 Issued
Array ( [id] => 15042755 [patent_doc_number] => 20190332382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => SIDE CACHE [patent_app_type] => utility [patent_app_number] => 15/967523 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967523 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967523
Side cache Apr 29, 2018 Issued
Array ( [id] => 18414791 [patent_doc_number] => 11669333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Method, apparatus, and system for reducing live readiness calculations in reservation stations [patent_app_type] => utility [patent_app_number] => 15/963126 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4557 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15963126 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/963126
Method, apparatus, and system for reducing live readiness calculations in reservation stations Apr 25, 2018 Issued
Menu