
Corey S. Faherty
Examiner (ID: 5369, Phone: (571)270-1319 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183 |
| Total Applications | 1281 |
| Issued Applications | 1020 |
| Pending Applications | 72 |
| Abandoned Applications | 208 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13526257
[patent_doc_number] => 20180314671
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-01
[patent_title] => Systems And Methods For Systolic Array Design From A High-Level Program
[patent_app_type] => utility
[patent_app_number] => 15/962916
[patent_app_country] => US
[patent_app_date] => 2018-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9691
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15962916
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/962916 | Systems and methods for systolic array design from a high-level program | Apr 24, 2018 | Issued |
Array
(
[id] => 16864494
[patent_doc_number] => 11023234
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Method and system for restructuring of collections for synchronization
[patent_app_type] => utility
[patent_app_number] => 15/952213
[patent_app_country] => US
[patent_app_date] => 2018-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 9175
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15952213
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/952213 | Method and system for restructuring of collections for synchronization | Apr 11, 2018 | Issued |
Array
(
[id] => 14966755
[patent_doc_number] => 20190310856
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-10
[patent_title] => EXECUTING INSTRUCTIONS BASED ON A SHARED PHYSICAL REGISTER
[patent_app_type] => utility
[patent_app_number] => 15/948220
[patent_app_country] => US
[patent_app_date] => 2018-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5520
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948220
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/948220 | EXECUTING INSTRUCTIONS BASED ON A SHARED PHYSICAL REGISTER | Apr 8, 2018 | Abandoned |
Array
(
[id] => 13497353
[patent_doc_number] => 20180300219
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-10-18
[patent_title] => CONTROL SYSTEM AND METHOD OF MEMORY ACCESS
[patent_app_type] => utility
[patent_app_number] => 15/945027
[patent_app_country] => US
[patent_app_date] => 2018-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6789
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945027
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/945027 | Control system and method of memory access | Apr 3, 2018 | Issued |
Array
(
[id] => 14935009
[patent_doc_number] => 20190303142
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-03
[patent_title] => EFFICIENT IMPLEMENTATION OF COMPLEX VECTOR FUSED MULTIPLY ADD AND COMPLEX VECTOR MULTIPLY
[patent_app_type] => utility
[patent_app_number] => 15/941531
[patent_app_country] => US
[patent_app_date] => 2018-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19658
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941531
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/941531 | Efficient implementation of complex vector fused multiply add and complex vector multiply | Mar 29, 2018 | Issued |
Array
(
[id] => 13906075
[patent_doc_number] => 20190042242
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-07
[patent_title] => INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECISION INPUT OPERANDS
[patent_app_type] => utility
[patent_app_number] => 15/940774
[patent_app_country] => US
[patent_app_date] => 2018-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17737
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15940774
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/940774 | Instructions for fused multiply-add operations with variable precision input operands | Mar 28, 2018 | Issued |
Array
(
[id] => 13448897
[patent_doc_number] => 20180275991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-27
[patent_title] => COMPILER-ASSISTED INTER-SIMD-GROUP REGISTER SHARING
[patent_app_type] => utility
[patent_app_number] => 15/935399
[patent_app_country] => US
[patent_app_date] => 2018-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7057
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15935399
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/935399 | Compiler-assisted inter-SIMD-group register sharing | Mar 25, 2018 | Issued |
Array
(
[id] => 15919417
[patent_doc_number] => 10656947
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-19
[patent_title] => Processor to perform a bit range isolation instruction
[patent_app_type] => utility
[patent_app_number] => 15/921134
[patent_app_country] => US
[patent_app_date] => 2018-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 9260
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15921134
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/921134 | Processor to perform a bit range isolation instruction | Mar 13, 2018 | Issued |
Array
(
[id] => 14202731
[patent_doc_number] => 10268481
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-23
[patent_title] => Load/store unit for a processor, and applications thereof
[patent_app_type] => utility
[patent_app_number] => 15/918106
[patent_app_country] => US
[patent_app_date] => 2018-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 10568
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15918106
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/918106 | Load/store unit for a processor, and applications thereof | Mar 11, 2018 | Issued |
Array
(
[id] => 13432767
[patent_doc_number] => 20180267926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-20
[patent_title] => ARITHMETIC PROCESSING DEVICE, INFORMATION PROCESSING APPARATUS, AND CONTROL METHOD OF THE ARITHMETIC PROCESSING DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/908879
[patent_app_country] => US
[patent_app_date] => 2018-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9910
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15908879
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/908879 | Arithmetic processing device, information processing apparatus, and control method of the arithmetic processing device | Feb 28, 2018 | Issued |
Array
(
[id] => 14825171
[patent_doc_number] => 10409593
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-10
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/905979
[patent_app_country] => US
[patent_app_date] => 2018-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 11104
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15905979
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/905979 | Semiconductor device | Feb 26, 2018 | Issued |
Array
(
[id] => 12868651
[patent_doc_number] => 20180181392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-28
[patent_title] => BIT-MASKED VARIABLE-PRECISION BARREL SHIFTER
[patent_app_type] => utility
[patent_app_number] => 15/901873
[patent_app_country] => US
[patent_app_date] => 2018-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9441
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15901873
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/901873 | Bit-masked variable-precision barrel shifter | Feb 20, 2018 | Issued |
Array
(
[id] => 13376133
[patent_doc_number] => 20180239608
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-23
[patent_title] => Super-Thread Processor
[patent_app_type] => utility
[patent_app_number] => 15/900760
[patent_app_country] => US
[patent_app_date] => 2018-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8031
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900760
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/900760 | Super-thread processor | Feb 19, 2018 | Issued |
Array
(
[id] => 12845074
[patent_doc_number] => 20180173531
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => VARIABLE REGISTER AND IMMEDIATE FIELD ENCODING IN AN INSTRUCTION SET ARCHITECTURE
[patent_app_type] => utility
[patent_app_number] => 15/898752
[patent_app_country] => US
[patent_app_date] => 2018-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7944
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898752
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/898752 | Variable register and immediate field encoding in an instruction set architecture | Feb 18, 2018 | Issued |
Array
(
[id] => 14825173
[patent_doc_number] => 10409594
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-09-10
[patent_title] => Processing circuit and control method of processing circuit
[patent_app_type] => utility
[patent_app_number] => 15/898260
[patent_app_country] => US
[patent_app_date] => 2018-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 11662
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 311
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898260
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/898260 | Processing circuit and control method of processing circuit | Feb 15, 2018 | Issued |
Array
(
[id] => 13347327
[patent_doc_number] => 20180225203
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-09
[patent_title] => DIADIC MEMORY OPERATIONS AND EXPANDED MEMORY FRONTEND OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 15/890580
[patent_app_country] => US
[patent_app_date] => 2018-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1781
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890580
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/890580 | Diadic memory operations and expanded memory frontend operations | Feb 6, 2018 | Issued |
Array
(
[id] => 14218567
[patent_doc_number] => 20190121668
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-25
[patent_title] => SCHEDULING TASKS IN A MULTI-THREADED PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 15/885925
[patent_app_country] => US
[patent_app_date] => 2018-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9772
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885925
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/885925 | Scheduling tasks in a multi-threaded processor | Jan 31, 2018 | Issued |
Array
(
[id] => 14218789
[patent_doc_number] => 20190121779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-25
[patent_title] => CONTROLLING TIMING IN COMPUTER PROCESSING
[patent_app_type] => utility
[patent_app_number] => 15/886340
[patent_app_country] => US
[patent_app_date] => 2018-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10241
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886340
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/886340 | Controlling timing in computer processing | Jan 31, 2018 | Issued |
Array
(
[id] => 15516769
[patent_doc_number] => 10564970
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-18
[patent_title] => Synchronization in a multi-tile processing arrangement
[patent_app_type] => utility
[patent_app_number] => 15/886099
[patent_app_country] => US
[patent_app_date] => 2018-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 20453
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886099
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/886099 | Synchronization in a multi-tile processing arrangement | Jan 31, 2018 | Issued |
Array
(
[id] => 16864548
[patent_doc_number] => 11023290
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Synchronization amongst processor tiles
[patent_app_type] => utility
[patent_app_number] => 15/885972
[patent_app_country] => US
[patent_app_date] => 2018-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 25508
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15885972
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/885972 | Synchronization amongst processor tiles | Jan 31, 2018 | Issued |