Search

Corey S. Faherty

Examiner (ID: 5369, Phone: (571)270-1319 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
1281
Issued Applications
1020
Pending Applications
72
Abandoned Applications
208

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19413807 [patent_doc_number] => 12079627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-09-03 [patent_title] => Predicated compare-exchange-shuffle instruction for parallel processor [patent_app_type] => utility [patent_app_number] => 18/189115 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6595 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18189115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/189115
Predicated compare-exchange-shuffle instruction for parallel processor Mar 22, 2023 Issued
Array ( [id] => 19765029 [patent_doc_number] => 12223320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-02-11 [patent_title] => Family of processors of different types configured for executing a common instruction set and method for executing instructions from the common instruction set using a processor of a specific processor type [patent_app_type] => utility [patent_app_number] => 18/188769 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 21421 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18188769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/188769
Family of processors of different types configured for executing a common instruction set and method for executing instructions from the common instruction set using a processor of a specific processor type Mar 22, 2023 Issued
Array ( [id] => 20960201 [patent_doc_number] => 12730638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-08 [patent_title] => Exception return state lock parameter [patent_app_type] => utility [patent_app_number] => 18/859256 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 11011 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18859256 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/859256
EXCEPTION RETURN STATE LOCK PARAMETER Mar 16, 2023 Pending
Array ( [id] => 18711225 [patent_doc_number] => 20230333854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => PERFORMANCE SCALING FOR BINARY TRANSLATION [patent_app_type] => utility [patent_app_number] => 18/185122 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18185122 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/185122
Performance scaling for binary translation Mar 15, 2023 Issued
Array ( [id] => 19451018 [patent_doc_number] => 20240311148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => INFERENCE PROCESSING OF DECISION TREE MODELS USING VECTOR INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/183187 [patent_app_country] => US [patent_app_date] => 2023-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18183187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/183187
Inference processing of decision tree models using vector instructions Mar 13, 2023 Issued
Array ( [id] => 19434580 [patent_doc_number] => 20240303078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => FRESHNESS AND GRAVITY OF DATA OPERATORS EXECUTING IN NEAR MEMORY COMPUTE IN SCALABLE DISAGGREGATED MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/181307 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181307 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/181307
Freshness and gravity of data operators executing in near memory compute in scalable disaggregated memory architectures Mar 8, 2023 Issued
Array ( [id] => 19581687 [patent_doc_number] => 12147805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Monitoring of program instructions [patent_app_type] => utility [patent_app_number] => 18/117186 [patent_app_country] => US [patent_app_date] => 2023-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18117186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/117186
Monitoring of program instructions Mar 2, 2023 Issued
Array ( [id] => 19740225 [patent_doc_number] => 12217060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-02-04 [patent_title] => Instruction fusion [patent_app_type] => utility [patent_app_number] => 18/176457 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 16894 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176457 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176457
Instruction fusion Feb 27, 2023 Issued
Array ( [id] => 18832541 [patent_doc_number] => 20230401068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => METHOD FOR IMPROVING ACCURACY OF LOOP BRANCH PREDICTION [patent_app_type] => utility [patent_app_number] => 18/115049 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 496 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18115049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/115049
Method for improving accuracy of loop branch prediction Feb 27, 2023 Issued
Array ( [id] => 18454180 [patent_doc_number] => 20230195460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => METHOD PERFORMED BY A MICROCONTROLLER FOR MANAGING A NOP INSTRUCTION AND CORRESPONDING MICROCONTROLLER [patent_app_type] => utility [patent_app_number] => 18/173782 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18173782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/173782
Method performed by a microcontroller for managing a NOP instruction and corresponding microcontroller Feb 23, 2023 Issued
Array ( [id] => 18499213 [patent_doc_number] => 20230221957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => INLINE DATA INSPECTION FOR WORKLOAD SIMPLIFICATION [patent_app_type] => utility [patent_app_number] => 18/112923 [patent_app_country] => US [patent_app_date] => 2023-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18112923 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/112923
Inline data inspection for workload simplification Feb 21, 2023 Issued
Array ( [id] => 19391379 [patent_doc_number] => 20240281249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => LOAD STORE CACHE MICROARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/170808 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 52133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170808 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170808
LOAD STORE CACHE MICROARCHITECTURE Feb 16, 2023 Pending
Array ( [id] => 19136888 [patent_doc_number] => 11971846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Logic unit for a reconfigurable processor [patent_app_type] => utility [patent_app_number] => 18/109817 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7222 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109817
Logic unit for a reconfigurable processor Feb 13, 2023 Issued
Array ( [id] => 18982539 [patent_doc_number] => 11907717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Techniques for efficiently transferring data to a processor [patent_app_type] => utility [patent_app_number] => 18/107374 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 18274 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107374 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/107374
Techniques for efficiently transferring data to a processor Feb 7, 2023 Issued
Array ( [id] => 18438282 [patent_doc_number] => 20230185577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => Communication in a Computer Having Multiple Processors [patent_app_type] => utility [patent_app_number] => 18/164202 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164202
Communication in a computer having multiple processors Feb 2, 2023 Issued
Array ( [id] => 19347321 [patent_doc_number] => 20240256284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEARCHING AN ARRAY OF MULTI-BYTE ELEMENTS USING AN N-BYTE SEARCH INSTRUCTION [patent_app_type] => utility [patent_app_number] => 18/102050 [patent_app_country] => US [patent_app_date] => 2023-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18102050 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/102050
Searching an array of multi-byte elements using an n-byte search instruction Jan 25, 2023 Issued
Array ( [id] => 19347318 [patent_doc_number] => 20240256281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => TECHNIQUE FOR IMPROVING EFFICIENCY OF DATA PROCESSING OPERATIONS IN AN APPARATUS THAT EMPLOYS REGISTER RENAMING [patent_app_type] => utility [patent_app_number] => 18/101726 [patent_app_country] => US [patent_app_date] => 2023-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18101726 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/101726
Technique for improving efficiency of data processing operations in an apparatus that employs register renaming Jan 25, 2023 Issued
Array ( [id] => 19566324 [patent_doc_number] => 12141095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Systolic array, systolic array system, computation method, device, and storage medium [patent_app_type] => utility [patent_app_number] => 18/158711 [patent_app_country] => US [patent_app_date] => 2023-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 15522 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18158711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/158711
Systolic array, systolic array system, computation method, device, and storage medium Jan 23, 2023 Issued
Array ( [id] => 19015232 [patent_doc_number] => 11922166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Vector SIMD VLIW data path architecture [patent_app_type] => utility [patent_app_number] => 18/097552 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 10397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097552 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/097552
Vector SIMD VLIW data path architecture Jan 16, 2023 Issued
Array ( [id] => 19251012 [patent_doc_number] => 20240202002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => METHODS AND APPARATUSES FOR INSTRUCTIONS INCLUDING A MISPREDICTION HANDLING HINT TO REDUCE A BRANCH MISPREDICTION PENALTY [patent_app_type] => utility [patent_app_number] => 18/067577 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067577 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067577
METHODS AND APPARATUSES FOR INSTRUCTIONS INCLUDING A MISPREDICTION HANDLING HINT TO REDUCE A BRANCH MISPREDICTION PENALTY Dec 15, 2022 Pending
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