Search

Cory W. Eskridge

Examiner (ID: 14658, Phone: (571)272-0543 , Office: P/2898 )

Most Active Art Unit
3624
Art Unit(s)
2898, 3624
Total Applications
814
Issued Applications
585
Pending Applications
77
Abandoned Applications
174

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14125543 [patent_doc_number] => 10249635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Three-dimensional semiconductor memory device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/822860 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 94 [patent_figures_cnt] => 99 [patent_no_of_words] => 13896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822860 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/822860
Three-dimensional semiconductor memory device and method for manufacturing the same Nov 26, 2017 Issued
Array ( [id] => 14110503 [patent_doc_number] => 20190096927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => MANUFACTURING METHOD OF THIN FILM TRANSISTOR AND MASK [patent_app_type] => utility [patent_app_number] => 15/744174 [patent_app_country] => US [patent_app_date] => 2017-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15744174 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/744174
MANUFACTURING METHOD OF THIN FILM TRANSISTOR AND MASK Nov 23, 2017 Abandoned
Array ( [id] => 12615309 [patent_doc_number] => 20180096933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM [patent_app_type] => utility [patent_app_number] => 15/820602 [patent_app_country] => US [patent_app_date] => 2017-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15820602 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/820602
Method to reduce resistance for a copper (Cu) interconnect landing on multilayered metal contacts, and semiconductor structures formed therefrom Nov 21, 2017 Issued
Array ( [id] => 14920545 [patent_doc_number] => 10431600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Method for manufacturing a semiconductor device including a metal oxide film [patent_app_type] => utility [patent_app_number] => 15/819201 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 64 [patent_no_of_words] => 36395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819201 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819201
Method for manufacturing a semiconductor device including a metal oxide film Nov 20, 2017 Issued
Array ( [id] => 14284963 [patent_doc_number] => 20190139766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 15/808359 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808359 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/808359
SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING THE SAME Nov 8, 2017 Abandoned
Array ( [id] => 12236329 [patent_doc_number] => 20180069192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/808250 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4629 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808250 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/808250
Display device with overlapping substrate Nov 8, 2017 Issued
Array ( [id] => 12800515 [patent_doc_number] => 20180158674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => AROMATIC RESINS FOR UNDERLAYERS [patent_app_type] => utility [patent_app_number] => 15/802089 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802089 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802089
Aromatic resins for underlayers Nov 1, 2017 Issued
Array ( [id] => 14397927 [patent_doc_number] => 10312255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Semiconductor device and method for manufacturing same [patent_app_type] => utility [patent_app_number] => 15/800162 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 76 [patent_no_of_words] => 17416 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800162 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800162
Semiconductor device and method for manufacturing same Oct 31, 2017 Issued
Array ( [id] => 12668809 [patent_doc_number] => 20180114769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => Chip Packaging Structure and Related Inner Lead Bonding Method [patent_app_type] => utility [patent_app_number] => 15/792767 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792767 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/792767
Chip Packaging Structure and Related Inner Lead Bonding Method Oct 24, 2017 Abandoned
Array ( [id] => 12185231 [patent_doc_number] => 20180044167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'MEMS DEVICE AND PROCESS' [patent_app_type] => utility [patent_app_number] => 15/792197 [patent_app_country] => US [patent_app_date] => 2017-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9973 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15792197 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/792197
MEMS DEVICE AND PROCESS Oct 23, 2017 Abandoned
Array ( [id] => 12181757 [patent_doc_number] => 20180040693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION BETWEEN FIN-SHAPED STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/786611 [patent_app_country] => US [patent_app_date] => 2017-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2518 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15786611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/786611
Method for fabricating shallow trench isolation between fin-shaped structures Oct 17, 2017 Issued
Array ( [id] => 13121963 [patent_doc_number] => 10079339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-18 [patent_title] => Magnetoresistive stack/structure and method of manufacturing same [patent_app_type] => utility [patent_app_number] => 15/727905 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 80 [patent_figures_cnt] => 82 [patent_no_of_words] => 12728 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727905 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727905
Magnetoresistive stack/structure and method of manufacturing same Oct 8, 2017 Issued
Array ( [id] => 12154744 [patent_doc_number] => 20180026008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => '3D Semiconductor Package Interposer with Die Cavity' [patent_app_type] => utility [patent_app_number] => 15/722983 [patent_app_country] => US [patent_app_date] => 2017-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722983 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/722983
3D semiconductor package interposer with die cavity Oct 1, 2017 Issued
Array ( [id] => 12604083 [patent_doc_number] => 20180093191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => APPARATUS FOR GENERATING GAME MANAGEMENT SCENARIO AND METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/720138 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720138 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720138
APPARATUS FOR GENERATING GAME MANAGEMENT SCENARIO AND METHOD USING THE SAME Sep 28, 2017 Abandoned
Array ( [id] => 13995947 [patent_doc_number] => 20190067131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => Interconnect Structure For Fin-Like Field Effect Transistor [patent_app_type] => utility [patent_app_number] => 15/691452 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691452 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691452
Interconnect structure for fin-like field effect transistor Aug 29, 2017 Issued
Array ( [id] => 12894910 [patent_doc_number] => 20180190145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => WORK SUPPORT DEVICE, WORK SUPPORT METHOD, AND COMPUTER PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 15/690796 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690796 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690796
WORK SUPPORT DEVICE, WORK SUPPORT METHOD, AND COMPUTER PROGRAM PRODUCT Aug 29, 2017 Abandoned
Array ( [id] => 17202688 [patent_doc_number] => 20210342783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => SYSTEM AND METHOD OF AUTOMATED EXTRACTION AND VISUALIZATION OF KNOWLEDGE ABOUT ENTERPRISE TECHNOLOGY, PERSONNEL AND BUSINESS FUNCTIONS [patent_app_type] => utility [patent_app_number] => 16/325818 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16325818 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/325818
SYSTEM AND METHOD OF AUTOMATED EXTRACTION AND VISUALIZATION OF KNOWLEDGE ABOUT ENTERPRISE TECHNOLOGY, PERSONNEL AND BUSINESS FUNCTIONS Aug 15, 2017 Abandoned
Array ( [id] => 12187989 [patent_doc_number] => 20180046925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING CLOSING METRICS' [patent_app_type] => utility [patent_app_number] => 15/667666 [patent_app_country] => US [patent_app_date] => 2017-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 20183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15667666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/667666
Method, apparatus, and computer program product for determining closing metrics Aug 2, 2017 Issued
Array ( [id] => 18136648 [patent_doc_number] => 11562331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-24 [patent_title] => Scheduling a subsequent meeting related to a previous meeting [patent_app_type] => utility [patent_app_number] => 15/662488 [patent_app_country] => US [patent_app_date] => 2017-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 19137 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15662488 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/662488
Scheduling a subsequent meeting related to a previous meeting Jul 27, 2017 Issued
Array ( [id] => 12161665 [patent_doc_number] => 20180032931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'RESOURCE MONITORING METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/661095 [patent_app_country] => US [patent_app_date] => 2017-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10364 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15661095 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/661095
RESOURCE MONITORING METHOD AND SYSTEM Jul 26, 2017 Abandoned
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