
Courtney L. Smith
Examiner (ID: 14799, Phone: (571)272-9094 , Office: P/2835 )
| Most Active Art Unit | 2835 |
| Art Unit(s) | 2809, 2835 |
| Total Applications | 1615 |
| Issued Applications | 1337 |
| Pending Applications | 95 |
| Abandoned Applications | 217 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18983588
[patent_doc_number] => 11908777
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-20
[patent_title] => Semiconductor package with plurality of leads and sealing resin
[patent_app_type] => utility
[patent_app_number] => 17/826975
[patent_app_country] => US
[patent_app_date] => 2022-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 29
[patent_no_of_words] => 11718
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/826975 | Semiconductor package with plurality of leads and sealing resin | May 26, 2022 | Issued |
Array
(
[id] => 18250764
[patent_doc_number] => 20230077803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/751740
[patent_app_country] => US
[patent_app_date] => 2022-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5908
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751740
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/751740 | Semiconductor devices including a through-hole electrode | May 23, 2022 | Issued |
Array
(
[id] => 18645663
[patent_doc_number] => 11769742
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-26
[patent_title] => Semiconductor chip and semiconductor package including the same
[patent_app_type] => utility
[patent_app_number] => 17/747190
[patent_app_country] => US
[patent_app_date] => 2022-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 22
[patent_no_of_words] => 14816
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747190
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/747190 | Semiconductor chip and semiconductor package including the same | May 17, 2022 | Issued |
Array
(
[id] => 17840754
[patent_doc_number] => 20220278060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => MOLDED SEMICONDUCTOR PACKAGE WITH HIGH VOLTAGE ISOLATION
[patent_app_type] => utility
[patent_app_number] => 17/746306
[patent_app_country] => US
[patent_app_date] => 2022-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5727
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746306
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/746306 | Molded semiconductor package with high voltage isolation | May 16, 2022 | Issued |
Array
(
[id] => 17949227
[patent_doc_number] => 20220336246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => METHOD FOR SUBSTRATE REGISTRATION AND ANCHORING IN INKJET PRINTING
[patent_app_type] => utility
[patent_app_number] => 17/735018
[patent_app_country] => US
[patent_app_date] => 2022-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5043
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735018
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/735018 | Method for substrate registration and anchoring in inkjet printing | May 1, 2022 | Issued |
Array
(
[id] => 18721546
[patent_doc_number] => 11798903
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-24
[patent_title] => Methods of forming microvias with reduced diameter
[patent_app_type] => utility
[patent_app_number] => 17/725003
[patent_app_country] => US
[patent_app_date] => 2022-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 5316
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725003
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/725003 | Methods of forming microvias with reduced diameter | Apr 19, 2022 | Issued |
Array
(
[id] => 18623852
[patent_doc_number] => 11756908
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-12
[patent_title] => Package substrate including a redistribution pad extending from a redistribution layer and including segmenting grooves along a redial direction thereof and semiconductor package including the same
[patent_app_type] => utility
[patent_app_number] => 17/718639
[patent_app_country] => US
[patent_app_date] => 2022-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 6666
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718639
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/718639 | Package substrate including a redistribution pad extending from a redistribution layer and including segmenting grooves along a redial direction thereof and semiconductor package including the same | Apr 11, 2022 | Issued |
Array
(
[id] => 18735670
[patent_doc_number] => 11804411
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-31
[patent_title] => Secure inspection and marking of semiconductor wafers for trusted manufacturing thereof
[patent_app_type] => utility
[patent_app_number] => 17/718390
[patent_app_country] => US
[patent_app_date] => 2022-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 8933
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718390
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/718390 | Secure inspection and marking of semiconductor wafers for trusted manufacturing thereof | Apr 11, 2022 | Issued |
Array
(
[id] => 18423982
[patent_doc_number] => 20230178446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-08
[patent_title] => Highly Protective Wafer Edge Sidewall Protection Layer
[patent_app_type] => utility
[patent_app_number] => 17/657184
[patent_app_country] => US
[patent_app_date] => 2022-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7724
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657184
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/657184 | Highly protective wafer edge sidewall protection layer | Mar 29, 2022 | Issued |
Array
(
[id] => 17723463
[patent_doc_number] => 20220216185
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-07
[patent_title] => BACKSIDE CONTACT TO IMPROVE THERMAL DISSIPATION AWAY FROM SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/703088
[patent_app_country] => US
[patent_app_date] => 2022-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10063
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703088
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/703088 | Backside contact to improve thermal dissipation away from semiconductor devices | Mar 23, 2022 | Issued |
Array
(
[id] => 19935304
[patent_doc_number] => 12308514
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-20
[patent_title] => Thermal and electrical insulation structure
[patent_app_type] => utility
[patent_app_number] => 17/701340
[patent_app_country] => US
[patent_app_date] => 2022-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 919
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701340
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/701340 | Thermal and electrical insulation structure | Mar 21, 2022 | Issued |
Array
(
[id] => 19918614
[patent_doc_number] => 12293990
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-06
[patent_title] => Semiconductor integrated circuit comprising master chip with first buffer circuit and slave chiip with second buffer circuit
[patent_app_type] => utility
[patent_app_number] => 17/700965
[patent_app_country] => US
[patent_app_date] => 2022-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 0
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17700965
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/700965 | Semiconductor integrated circuit comprising master chip with first buffer circuit and slave chiip with second buffer circuit | Mar 21, 2022 | Issued |
Array
(
[id] => 17708750
[patent_doc_number] => 20220208758
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-30
[patent_title] => METHODS FOR PILLAR CONNECTION ON FRONTSIDE AND PASSIVE DEVICE INTEGRATION ON BACKSIDE OF DIE
[patent_app_type] => utility
[patent_app_number] => 17/699680
[patent_app_country] => US
[patent_app_date] => 2022-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13798
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699680
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/699680 | Methods for pillar connection on frontside and passive device integration on backside of die | Mar 20, 2022 | Issued |
Array
(
[id] => 17708600
[patent_doc_number] => 20220208608
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-30
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/655075
[patent_app_country] => US
[patent_app_date] => 2022-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11048
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655075
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/655075 | Semiconductor device and manufacturing method of semiconductor device including a through electrode for connection of wirings | Mar 15, 2022 | Issued |
Array
(
[id] => 19957358
[patent_doc_number] => 12327777
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-10
[patent_title] => Semiconductor package structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/691149
[patent_app_country] => US
[patent_app_date] => 2022-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 2351
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17691149
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/691149 | Semiconductor package structure and manufacturing method thereof | Mar 9, 2022 | Issued |
Array
(
[id] => 18645645
[patent_doc_number] => 11769724
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-26
[patent_title] => Package having different metal densities in different regions and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/684431
[patent_app_country] => US
[patent_app_date] => 2022-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 9090
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17684431
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/684431 | Package having different metal densities in different regions and manufacturing method thereof | Mar 1, 2022 | Issued |
Array
(
[id] => 17645320
[patent_doc_number] => 20220173059
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-02
[patent_title] => BONDING STRUCTURE AND METHOD OF FORMING SAME
[patent_app_type] => utility
[patent_app_number] => 17/673953
[patent_app_country] => US
[patent_app_date] => 2022-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15915
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673953
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/673953 | Bonding structure and method of forming same | Feb 16, 2022 | Issued |
Array
(
[id] => 17645337
[patent_doc_number] => 20220173076
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-02
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/674337
[patent_app_country] => US
[patent_app_date] => 2022-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8153
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674337
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/674337 | Method of manufacturing a semiconductor package including a dam structure surrounding a semiconductor chip mounting region | Feb 16, 2022 | Issued |
Array
(
[id] => 17780219
[patent_doc_number] => 20220246569
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-04
[patent_title] => COMBINATION-BONDED DIE PAIR PACKAGING AND ASSOCIATED SYSTEMS AND METHODS
[patent_app_type] => utility
[patent_app_number] => 17/674487
[patent_app_country] => US
[patent_app_date] => 2022-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2978
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674487
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/674487 | Combination-bonded die pair packaging and associated systems and methods | Feb 16, 2022 | Issued |
Array
(
[id] => 19858286
[patent_doc_number] => 12261137
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-25
[patent_title] => Bonding structure and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 17/668785
[patent_app_country] => US
[patent_app_date] => 2022-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 4642
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668785
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/668785 | Bonding structure and method for forming the same | Feb 9, 2022 | Issued |