Search

Courtney L. Smith

Examiner (ID: 14799, Phone: (571)272-9094 , Office: P/2835 )

Most Active Art Unit
2835
Art Unit(s)
2809, 2835
Total Applications
1615
Issued Applications
1337
Pending Applications
95
Abandoned Applications
217

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17615471 [patent_doc_number] => 20220157751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => BOND PAD WITH ENHANCED RELIABILITY [patent_app_type] => utility [patent_app_number] => 17/590411 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/590411
Bond pad with enhanced reliability Jan 31, 2022 Issued
Array ( [id] => 18533282 [patent_doc_number] => 20230238358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => Stacking of integrated circuit dies [patent_app_type] => utility [patent_app_number] => 17/584450 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584450
Mirror image of geometrical patterns in stacked integrated circuit dies Jan 25, 2022 Issued
Array ( [id] => 19926345 [patent_doc_number] => 12300639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Seamless bonding layers in semiconductor packages and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/580942 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 33 [patent_no_of_words] => 5630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580942
Seamless bonding layers in semiconductor packages and methods of forming the same Jan 20, 2022 Issued
Array ( [id] => 19376719 [patent_doc_number] => 12068299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/580370 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5608 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580370
Semiconductor device and method of manufacturing the same Jan 19, 2022 Issued
Array ( [id] => 20146847 [patent_doc_number] => 12381194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Package having embedded decoupling capacitor and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/578469 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578469
Package having embedded decoupling capacitor and method of forming the same Jan 18, 2022 Issued
Array ( [id] => 18125321 [patent_doc_number] => 20230010936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/568355 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568355 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568355
Semiconductor chip having a through electrode and semiconductor package including the semiconductor chip Jan 3, 2022 Issued
Array ( [id] => 19886930 [patent_doc_number] => 12272661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Semiconductor package including semiconductor chips stacked via conductive bumps [patent_app_type] => utility [patent_app_number] => 17/564689 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 7944 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564689
Semiconductor package including semiconductor chips stacked via conductive bumps Dec 28, 2021 Issued
Array ( [id] => 17708694 [patent_doc_number] => 20220208702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => STRUCTURE WITH CONDUCTIVE FEATURE AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/564550 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564550 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564550
Structure with conductive feature and method of forming same Dec 28, 2021 Issued
Array ( [id] => 18473239 [patent_doc_number] => 20230207527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => THROUGH-SILICON VIA LAYOUT FOR MULTI-DIE INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/564137 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564137 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564137
Through-silicon via layout for multi-die integrated circuits Dec 27, 2021 Issued
Array ( [id] => 18995019 [patent_doc_number] => 11911839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Low temperature hybrid bonding [patent_app_type] => utility [patent_app_number] => 17/563830 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 33 [patent_no_of_words] => 7441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563830
Low temperature hybrid bonding Dec 27, 2021 Issued
Array ( [id] => 19244499 [patent_doc_number] => 12014953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Semiconductor device mitigating parasitic capacitance and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/555844 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555844 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555844
Semiconductor device mitigating parasitic capacitance and method of fabricating the same Dec 19, 2021 Issued
Array ( [id] => 18927269 [patent_doc_number] => 20240030273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => LIGHT SOURCE MODULE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/622816 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17622816 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/622816
Light source module and display device Dec 16, 2021 Issued
Array ( [id] => 19781638 [patent_doc_number] => 12230677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Quantum structure getter for radiation hardened transistors [patent_app_type] => utility [patent_app_number] => 17/553038 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4320 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/553038
Quantum structure getter for radiation hardened transistors Dec 15, 2021 Issued
Array ( [id] => 19721956 [patent_doc_number] => 12207515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Display apparatus and multi-screen display apparatus including the same [patent_app_type] => utility [patent_app_number] => 17/551549 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 34930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551549 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551549
Display apparatus and multi-screen display apparatus including the same Dec 14, 2021 Issued
Array ( [id] => 19183788 [patent_doc_number] => 11990389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Semiconductor package including embedded cooling structure [patent_app_type] => utility [patent_app_number] => 17/550347 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3709 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550347 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550347
Semiconductor package including embedded cooling structure Dec 13, 2021 Issued
Array ( [id] => 17676750 [patent_doc_number] => 20220189917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => THROUGH-SILICON TRANSMISSION LINES AND OTHER STRUCTURES ENABLED BY SAME [patent_app_type] => utility [patent_app_number] => 17/548050 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548050 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548050
Through-silicon transmission lines and other structures enabled by same Dec 9, 2021 Issued
Array ( [id] => 17486078 [patent_doc_number] => 20220093582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/541869 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/541869
Semiconductor package including a first semiconductor chip with a plurality of first chip pads directly bonded to a plurality of second chip pads of an upper semiconductor chip Dec 2, 2021 Issued
Array ( [id] => 18827706 [patent_doc_number] => 11842996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Transistor with odd-mode oscillation stabilization circuit [patent_app_type] => utility [patent_app_number] => 17/456434 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 10070 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456434
Transistor with odd-mode oscillation stabilization circuit Nov 23, 2021 Issued
Array ( [id] => 17869042 [patent_doc_number] => 20220291779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/531853 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531853
Display device Nov 21, 2021 Issued
Array ( [id] => 20204177 [patent_doc_number] => 12406962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Power delivery through capacitor-dies in a multi-layered microelectronic assembly [patent_app_type] => utility [patent_app_number] => 17/531374 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 12147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531374
Power delivery through capacitor-dies in a multi-layered microelectronic assembly Nov 18, 2021 Issued
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