Search

Courtney L. Smith

Examiner (ID: 14799, Phone: (571)272-9094 , Office: P/2835 )

Most Active Art Unit
2835
Art Unit(s)
2809, 2835
Total Applications
1615
Issued Applications
1337
Pending Applications
95
Abandoned Applications
217

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17085534 [patent_doc_number] => 20210280541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER AND A BUMP [patent_app_type] => utility [patent_app_number] => 17/328365 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17328365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/328365
Semiconductor devices including a thick metal layer and a bump May 23, 2021 Issued
Array ( [id] => 18131389 [patent_doc_number] => 11557606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof [patent_app_type] => utility [patent_app_number] => 17/329007 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 2720 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/329007
Epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof May 23, 2021 Issued
Array ( [id] => 18131355 [patent_doc_number] => 11557572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Semiconductor device with stacked dies and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/319257 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10761 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/319257
Semiconductor device with stacked dies and method for fabricating the same May 12, 2021 Issued
Array ( [id] => 18105577 [patent_doc_number] => 11545475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Integrated display devices [patent_app_type] => utility [patent_app_number] => 17/318736 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 11077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318736
Integrated display devices May 11, 2021 Issued
Array ( [id] => 18190637 [patent_doc_number] => 11581238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Heat spreading layer integrated within a composite IC die structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/318887 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 9260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318887
Heat spreading layer integrated within a composite IC die structure and methods of forming the same May 11, 2021 Issued
Array ( [id] => 18156299 [patent_doc_number] => 11569293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Micro-LED displays [patent_app_type] => utility [patent_app_number] => 17/316288 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316288 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316288
Micro-LED displays May 9, 2021 Issued
Array ( [id] => 17993445 [patent_doc_number] => 20220359482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => MEMORY AND LOGIC CHIP STACK WITH A TRANSLATOR CHIP [patent_app_type] => utility [patent_app_number] => 17/315965 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315965
Memory and logic chip stack with a translator chip May 9, 2021 Issued
Array ( [id] => 17738091 [patent_doc_number] => 20220223553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/315487 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315487 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315487
Semiconductor packages with stacked dies and methods of forming the same May 9, 2021 Issued
Array ( [id] => 17070924 [patent_doc_number] => 20210273141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => WHITE LED LIGHT SOURCE AND METHOD OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 17/306605 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306605
WHITE LED LIGHT SOURCE AND METHOD OF MAKING SAME May 2, 2021 Abandoned
Array ( [id] => 18481241 [patent_doc_number] => 11694996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Semiconductor package including a pad contacting a via [patent_app_type] => utility [patent_app_number] => 17/245913 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 10496 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/245913
Semiconductor package including a pad contacting a via Apr 29, 2021 Issued
Array ( [id] => 18304445 [patent_doc_number] => 11626359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Three-dimensional integrated circuit (3D IC) power distribution network (PDN) capacitor integration [patent_app_type] => utility [patent_app_number] => 17/242083 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242083 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242083
Three-dimensional integrated circuit (3D IC) power distribution network (PDN) capacitor integration Apr 26, 2021 Issued
Array ( [id] => 18205490 [patent_doc_number] => 11587895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods [patent_app_type] => utility [patent_app_number] => 17/236425 [patent_app_country] => US [patent_app_date] => 2021-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 10396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17236425 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/236425
Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods Apr 20, 2021 Issued
Array ( [id] => 18913090 [patent_doc_number] => 11876078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Through-silicon via interconnection structure and methods for fabricating same [patent_app_type] => utility [patent_app_number] => 17/234554 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6996 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234554 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/234554
Through-silicon via interconnection structure and methods for fabricating same Apr 18, 2021 Issued
Array ( [id] => 17810943 [patent_doc_number] => 20220262778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => Deep Partition Power Delivery with Deep Trench Capacitor [patent_app_type] => utility [patent_app_number] => 17/232325 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232325
Deep partition power delivery with deep trench capacitor Apr 15, 2021 Issued
Array ( [id] => 19161356 [patent_doc_number] => 20240154063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/549479 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18549479 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/549479
SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS THEREOF Apr 14, 2021 Pending
Array ( [id] => 17917648 [patent_doc_number] => 20220320044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => BONDED WAFER DEVICE STRUCTURE AND METHODS FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/218401 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218401
Bonded wafer device structure and methods for making the same Mar 30, 2021 Issued
Array ( [id] => 16966256 [patent_doc_number] => 20210217755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/214710 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214710 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214710
Semiconductor memory having first and second memory cell regions separated by a third region along a bit line direction Mar 25, 2021 Issued
Array ( [id] => 18759860 [patent_doc_number] => 11810900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Semiconductor packages stacked by wafer bonding process and methods of manufacturing the semiconductor packages [patent_app_type] => utility [patent_app_number] => 17/209801 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8105 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209801
Semiconductor packages stacked by wafer bonding process and methods of manufacturing the semiconductor packages Mar 22, 2021 Issued
Array ( [id] => 18661446 [patent_doc_number] => 20230307460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => DISPLAY PANEL AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/286480 [patent_app_country] => US [patent_app_date] => 2021-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17286480 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/286480
Display panel and manufacturing method thereof Mar 21, 2021 Issued
Array ( [id] => 17463823 [patent_doc_number] => 20220077129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/204394 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204394 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/204394
Three-dimensional semiconductor memory device and electronic system including the same Mar 16, 2021 Issued
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