Search

Courtney L. Smith

Examiner (ID: 14799, Phone: (571)272-9094 , Office: P/2835 )

Most Active Art Unit
2835
Art Unit(s)
2809, 2835
Total Applications
1615
Issued Applications
1337
Pending Applications
95
Abandoned Applications
217

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18891044 [patent_doc_number] => 11869821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Semiconductor package having molding layer with inclined side wall [patent_app_type] => utility [patent_app_number] => 17/879272 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 14586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879272 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/879272
Semiconductor package having molding layer with inclined side wall Aug 1, 2022 Issued
Array ( [id] => 18040157 [patent_doc_number] => 20220384374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => Chiplets 3D SoIC System Integration and Fabrication Methods [patent_app_type] => utility [patent_app_number] => 17/815738 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815738 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815738
Chiplets 3D SoIC system integration and fabrication methods Jul 27, 2022 Issued
Array ( [id] => 20509303 [patent_doc_number] => 12543597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Partitioned overlapped copper-bonded interposers [patent_app_type] => utility [patent_app_number] => 17/872371 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872371
Partitioned overlapped copper-bonded interposers Jul 24, 2022 Issued
Array ( [id] => 18221734 [patent_doc_number] => 20230060728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SOC PMUT SUITABLE FOR HIGH-DENSITY SYSTEM INTEGRATION, ARRAY CHIP, AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/870810 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870810 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870810
SOC PMUT suitable for high-density system integration, array chip, and manufacturing method thereof Jul 20, 2022 Issued
Array ( [id] => 17993521 [patent_doc_number] => 20220359558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => BOUNDARY DESIGN TO REDUCE MEMORY ARRAY EDGE CMP DISHING EFFECT [patent_app_type] => utility [patent_app_number] => 17/866922 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866922 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866922
Boundary design to reduce memory array edge CMP dishing effect Jul 17, 2022 Issued
Array ( [id] => 18639569 [patent_doc_number] => 11764192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Semiconductor package including underfill material layer and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/861580 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 14093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861580 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861580
Semiconductor package including underfill material layer and method of forming the same Jul 10, 2022 Issued
Array ( [id] => 19484384 [patent_doc_number] => 20240332426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => THIN FILM SEMICONDUCTOR SWITCHING DEVICE [patent_app_type] => utility [patent_app_number] => 18/576205 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -38 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18576205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/576205
THIN FILM SEMICONDUCTOR SWITCHING DEVICE Jul 7, 2022 Pending
Array ( [id] => 20246130 [patent_doc_number] => 12426476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Display panel and display device [patent_app_type] => utility [patent_app_number] => 17/856592 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856592 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856592
Display panel and display device Jun 30, 2022 Issued
Array ( [id] => 19046733 [patent_doc_number] => 11935853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Memory devices with backside bond pads under a memory array [patent_app_type] => utility [patent_app_number] => 17/854428 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 4300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854428
Memory devices with backside bond pads under a memory array Jun 29, 2022 Issued
Array ( [id] => 18309565 [patent_doc_number] => 20230113465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/854659 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854659 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854659
Semiconductor package with bonding interface Jun 29, 2022 Issued
Array ( [id] => 17933302 [patent_doc_number] => 20220328428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MOISTURE BARRIER FOR BOND PADS AND INTEGRATED CIRCUIT HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/809257 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809257
Moisture barrier for bond pads and integrated circuit having the same Jun 26, 2022 Issued
Array ( [id] => 18866063 [patent_doc_number] => 20230420500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => CPP-AGNOSTIC SOURCE-DRAIN CONTACT FORMATION FOR GATE-ALL-AROUND DEVICES WITH DIELECTRIC ISOLATION [patent_app_type] => utility [patent_app_number] => 17/850475 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850475 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850475
CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation Jun 26, 2022 Issued
Array ( [id] => 19873719 [patent_doc_number] => 12266590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Dual side direct cooling semiconductor package [patent_app_type] => utility [patent_app_number] => 17/806961 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806961 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806961
Dual side direct cooling semiconductor package Jun 14, 2022 Issued
Array ( [id] => 18112939 [patent_doc_number] => 20230005819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => STACKABLE FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH THROUGH SILICON VIA (TSV) VERTICAL INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/841627 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841627 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/841627
Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects Jun 14, 2022 Issued
Array ( [id] => 20148274 [patent_doc_number] => 12382634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Semiconductor memory device that includes a plurality of first pillars, second pillars, and third pillars [patent_app_type] => utility [patent_app_number] => 17/840686 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 60 [patent_no_of_words] => 15151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/840686
Semiconductor memory device that includes a plurality of first pillars, second pillars, and third pillars Jun 14, 2022 Issued
Array ( [id] => 19223691 [patent_doc_number] => 20240188395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => DISPLAY PANEL AND DISPLAY TERMINAL [patent_app_type] => utility [patent_app_number] => 17/787516 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17787516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/787516
Display panel and display terminal Jun 7, 2022 Issued
Array ( [id] => 18797009 [patent_doc_number] => 11830844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/834923 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 42 [patent_no_of_words] => 17008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834923
Semiconductor structure Jun 6, 2022 Issued
Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826975
Semiconductor package with plurality of leads and sealing resin May 26, 2022 Issued
Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826975
Semiconductor package with plurality of leads and sealing resin May 26, 2022 Issued
Array ( [id] => 18983588 [patent_doc_number] => 11908777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor package with plurality of leads and sealing resin [patent_app_type] => utility [patent_app_number] => 17/826975 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 11718 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826975
Semiconductor package with plurality of leads and sealing resin May 26, 2022 Issued
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