Search

Craig A. Renner

Examiner (ID: 142, Phone: (571)272-7580 , Office: P/2688 )

Most Active Art Unit
2688
Art Unit(s)
2754, 2689, 2627, 2652, 2688, 2303, 2512
Total Applications
2133
Issued Applications
1663
Pending Applications
112
Abandoned Applications
378

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16896301 [patent_doc_number] => 11037863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/914628 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 11386 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914628 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914628
Semiconductor device Mar 6, 2018 Issued
Array ( [id] => 13436583 [patent_doc_number] => 20180269834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => VIBRATOR DEVICE, OSCILLATOR, ELECTRONIC DEVICE, AND VEHICLE [patent_app_type] => utility [patent_app_number] => 15/914606 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914606 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914606
Vibrator device, oscillator, electronic device, and vehicle Mar 6, 2018 Issued
Array ( [id] => 16881207 [patent_doc_number] => 11031364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Nanoparticle backside die adhesion layer [patent_app_type] => utility [patent_app_number] => 15/914761 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4187 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914761 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914761
Nanoparticle backside die adhesion layer Mar 6, 2018 Issued
Array ( [id] => 15791441 [patent_doc_number] => 10629452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Manufacturing method of a chip package structure [patent_app_type] => utility [patent_app_number] => 15/911290 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 31 [patent_no_of_words] => 8531 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911290 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/911290
Manufacturing method of a chip package structure Mar 4, 2018 Issued
Array ( [id] => 16553060 [patent_doc_number] => 10886225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => BEOL alternative metal interconnects: integration and process [patent_app_type] => utility [patent_app_number] => 15/912089 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7943 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15912089 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/912089
BEOL alternative metal interconnects: integration and process Mar 4, 2018 Issued
Array ( [id] => 14812815 [patent_doc_number] => 20190273017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => Method of Forming Contacts to an Embedded Semiconductor Die and Related Semiconductor Packages [patent_app_type] => utility [patent_app_number] => 15/912081 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15912081 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/912081
Method of forming contacts to an embedded semiconductor die and related semiconductor packages Mar 4, 2018 Issued
Array ( [id] => 14752951 [patent_doc_number] => 20190259649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => DUAL AIRGAP STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/901411 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15901411 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/901411
Dual airgap structure Feb 20, 2018 Issued
Array ( [id] => 13950789 [patent_doc_number] => 10211173 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-19 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/901366 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 5442 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15901366 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/901366
Semiconductor device and manufacturing method thereof Feb 20, 2018 Issued
Array ( [id] => 14459767 [patent_doc_number] => 10325857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Semiconductor device manufacturing method and semiconductor wafer [patent_app_type] => utility [patent_app_number] => 15/901437 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 67 [patent_no_of_words] => 6595 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15901437 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/901437
Semiconductor device manufacturing method and semiconductor wafer Feb 20, 2018 Issued
Array ( [id] => 12872818 [patent_doc_number] => 20180182781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => ARRAY SUBSTRATE AND METHOD OF MOUNTING INTEGRATED CIRCUIT USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/901846 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15901846 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/901846
Array substrate and method of mounting integrated circuit using the same Feb 20, 2018 Issued
Array ( [id] => 16973613 [patent_doc_number] => 11069593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/900885 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2783 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900885 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900885
Semiconductor device Feb 20, 2018 Issued
Array ( [id] => 15984869 [patent_doc_number] => 10672774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Bit line gate structure of dynamic random access memory (DRAM) and forming method thereof [patent_app_type] => utility [patent_app_number] => 15/900800 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2704 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900800 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900800
Bit line gate structure of dynamic random access memory (DRAM) and forming method thereof Feb 20, 2018 Issued
Array ( [id] => 13408183 [patent_doc_number] => 20180255634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => PACKAGED RF CIRCUITS AND RADIO UNIT [patent_app_type] => utility [patent_app_number] => 15/898870 [patent_app_country] => US [patent_app_date] => 2018-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898870 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/898870
PACKAGED RF CIRCUITS AND RADIO UNIT Feb 18, 2018 Abandoned
Array ( [id] => 14603487 [patent_doc_number] => 10354940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/898676 [patent_app_country] => US [patent_app_date] => 2018-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9054 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898676 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/898676
Semiconductor device Feb 18, 2018 Issued
Array ( [id] => 14542327 [patent_doc_number] => 20190206785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => ELECTRONIC DEVICES WITH BOND PADS FORMED ON A MOLYBDENUM LAYER [patent_app_type] => utility [patent_app_number] => 15/898694 [patent_app_country] => US [patent_app_date] => 2018-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15898694 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/898694
Electronic devices with bond pads formed on a molybdenum layer Feb 18, 2018 Issued
Array ( [id] => 13363773 [patent_doc_number] => 20180233426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => Chip scale package [patent_app_type] => utility [patent_app_number] => 15/932286 [patent_app_country] => US [patent_app_date] => 2018-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15932286 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/932286
Chip scale package Feb 15, 2018 Issued
Array ( [id] => 12848956 [patent_doc_number] => 20180174825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => INTEGRATED SYSTEM AND METHOD FOR SOURCE/DRAIN ENGINEERING [patent_app_type] => utility [patent_app_number] => 15/890117 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890117 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/890117
Integrated system and method for source/drain engineering Feb 5, 2018 Issued
Array ( [id] => 16402331 [patent_doc_number] => 20200343189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => ELECTRONIC MODULE [patent_app_type] => utility [patent_app_number] => 16/961628 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16961628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/961628
Electronic module Jan 16, 2018 Issued
Array ( [id] => 12738826 [patent_doc_number] => 20180138109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 15/871414 [patent_app_country] => US [patent_app_date] => 2018-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871414 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/871414
Semiconductor devices and methods of making the same Jan 14, 2018 Issued
Array ( [id] => 13909145 [patent_doc_number] => 20190043777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => SEMICONDUCTOR PACKAGE FOR INCREASING HEAT RADIATION EFFICIENCY [patent_app_type] => utility [patent_app_number] => 15/870902 [patent_app_country] => US [patent_app_date] => 2018-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870902 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/870902
SEMICONDUCTOR PACKAGE FOR INCREASING HEAT RADIATION EFFICIENCY Jan 12, 2018 Abandoned
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