Craig A. Renner

Array ( [id] => 11946014 [patent_doc_number] => 20170250165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'SEMICONDUCTOR PACKAGE ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 15/592488 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4341 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12989836 [patent_doc_number] => 20170345678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => INTEGRATED CIRCUIT PACKAGE CONFIGURATIONS TO REDUCE STIFFNESS [patent_app_type] => utility [patent_app_number] => 15/590890 [patent_app_country] => US [patent_app_date] => 2017-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15590890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12516648 [patent_doc_number] => 10003018 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-19 [patent_title] => Vertical multi-batch magnetic annealing systems for reduced footprint manufacturing environments [patent_app_type] => utility [patent_app_number] => 15/589613 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8790 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11869495 [patent_doc_number] => 20170236780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'INTEGRATED CIRCUIT HAVING IMPROVED ELECTROMIGRATION PERFORMANCE AND METHOD OF FORMING SAME' [patent_app_type] => utility [patent_app_number] => 15/485657 [patent_app_country] => US [patent_app_date] => 2017-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4000 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16770973 [patent_doc_number] => 10982064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Multilayer barrier films [patent_app_type] => utility [patent_app_number] => 16/086493 [patent_app_country] => US [patent_app_date] => 2017-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7961 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16086493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14137989 [patent_doc_number] => 20190103384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => Multi-LED System [patent_app_type] => utility [patent_app_number] => 16/086567 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16086567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11710558 [patent_doc_number] => 20170179057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF' [patent_app_type] => utility [patent_app_number] => 15/446169 [patent_app_country] => US [patent_app_date] => 2017-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3297 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15446169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14079325 [patent_doc_number] => 20190088550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => Composite Wafer, Semiconductor Device, Electronic Component and Method of Manufacturing a Semiconductor Device [patent_app_type] => utility [patent_app_number] => 16/081236 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16081236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11710584 [patent_doc_number] => 20170179083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Semiconductor Packaging Structure and Method' [patent_app_type] => utility [patent_app_number] => 15/443679 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14920379 [patent_doc_number] => 10431516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Semiconductor device and method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 15/438268 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 37 [patent_no_of_words] => 10611 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15438268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13695467 [patent_doc_number] => 20170358688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => TRANSISTOR ARRAY PANEL [patent_app_type] => utility [patent_app_number] => 15/436011 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12229863 [patent_doc_number] => 09917113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Array substrate and method of mounting integrated circuit using the same' [patent_app_type] => utility [patent_app_number] => 15/429411 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7455 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15429411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14459723 [patent_doc_number] => 10325835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Semiconductor devices and methods of making the same [patent_app_type] => utility [patent_app_number] => 15/421515 [patent_app_country] => US [patent_app_date] => 2017-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 7382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15421515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11630794 [patent_doc_number] => 20170140984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER' [patent_app_type] => utility [patent_app_number] => 15/420467 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3463 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15420467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13173813 [patent_doc_number] => 10103028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Contact integration and selective silicide formation methods [patent_app_type] => utility [patent_app_number] => 15/417638 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15417638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13878739 [patent_doc_number] => 20190035710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => BONDED BODY, POWER MODULE SUBSTRATE, METHOD FOR MANUFACTURING BONDED BODY, AND METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/070332 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16070332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11876439 [patent_doc_number] => 09748220 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-29 [patent_title] => 'Gate-bounded silicon controlled rectifier' [patent_app_type] => utility [patent_app_number] => 15/397741 [patent_app_country] => US [patent_app_date] => 2017-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6441 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11840326 [patent_doc_number] => 20170222046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/397677 [patent_app_country] => US [patent_app_date] => 2017-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13014 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13182361 [patent_doc_number] => 10106683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Resin composite, semiconductor device, and method of manufacturing the semiconductor device [patent_app_type] => utility [patent_app_number] => 15/397648 [patent_app_country] => US [patent_app_date] => 2017-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6500 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11502890 [patent_doc_number] => 20170077075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'Laser Marking in Packages' [patent_app_type] => utility [patent_app_number] => 15/361861 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15361861 [rel_patent_id] =>[rel_patent_doc_number] =>)