Search

Craig E O'connor

Examiner (ID: 8984)

Most Active Art Unit
3747
Art Unit(s)
3747
Total Applications
1
Issued Applications
1
Pending Applications
0
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10448173 [patent_doc_number] => 20150333187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/809984 [patent_app_country] => US [patent_app_date] => 2015-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14559 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14809984 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/809984
THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR Jul 26, 2015 Abandoned
Array ( [id] => 10426152 [patent_doc_number] => 20150311163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'Anchoring Structure and Intermeshing Structure' [patent_app_type] => utility [patent_app_number] => 14/791026 [patent_app_country] => US [patent_app_date] => 2015-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 38528 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14791026 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/791026
Anchoring Structure and Intermeshing Structure Jul 1, 2015 Abandoned
Array ( [id] => 13755525 [patent_doc_number] => 10170718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Electronic devices employing aligned organic polymers [patent_app_type] => utility [patent_app_number] => 14/725810 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6773 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14725810 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/725810
Electronic devices employing aligned organic polymers May 28, 2015 Issued
Array ( [id] => 11087878 [patent_doc_number] => 20160284846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'FORMING TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKING FAULT AND RESULTING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/667872 [patent_app_country] => US [patent_app_date] => 2015-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14667872 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/667872
FORMING TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKING FAULT AND RESULTING DEVICE Mar 24, 2015 Abandoned
Array ( [id] => 9901572 [patent_doc_number] => 20150056772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'SEMICONDUCTOR DEVICE COMPRISING BURIED GATE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/532762 [patent_app_country] => US [patent_app_date] => 2014-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3824 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14532762 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/532762
SEMICONDUCTOR DEVICE COMPRISING BURIED GATE AND METHOD FOR FABRICATING THE SAME Nov 3, 2014 Abandoned
Array ( [id] => 9901607 [patent_doc_number] => 20150056807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/531738 [patent_app_country] => US [patent_app_date] => 2014-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531738 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/531738
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Nov 2, 2014 Abandoned
Array ( [id] => 10772235 [patent_doc_number] => 20160118391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'DEUTERIUM ANNEAL OF SEMICONDUCTOR CHANNELS IN A THREE-DIMENSIONAL MEMORY STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/521136 [patent_app_country] => US [patent_app_date] => 2014-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14834 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14521136 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/521136
DEUTERIUM ANNEAL OF SEMICONDUCTOR CHANNELS IN A THREE-DIMENSIONAL MEMORY STRUCTURE Oct 21, 2014 Abandoned
Array ( [id] => 11010806 [patent_doc_number] => 20160207759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'MOLDED LEAD FRAME PACKAGE WITH EMBEDDED DIE' [patent_app_type] => utility [patent_app_number] => 14/915032 [patent_app_country] => US [patent_app_date] => 2014-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14915032 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/915032
Molded lead frame package with embedded die Aug 28, 2014 Issued
Array ( [id] => 10964712 [patent_doc_number] => 20140367744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'Monolithic Integrated Composite Group III-V and Group IV Semiconductor Device and IC' [patent_app_type] => utility [patent_app_number] => 14/472974 [patent_app_country] => US [patent_app_date] => 2014-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14472974 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/472974
Monolithic Integrated Composite Group III-V and Group IV Semiconductor Device and IC Aug 28, 2014 Abandoned
Array ( [id] => 10957964 [patent_doc_number] => 20140360988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'LASER DICING METHOD' [patent_app_type] => utility [patent_app_number] => 14/466755 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11402 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466755 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466755
LASER DICING METHOD Aug 21, 2014 Abandoned
Array ( [id] => 10958289 [patent_doc_number] => 20140361314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'SEMICONDUCTOR ALLOY FIN FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/466484 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7051 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466484 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466484
SEMICONDUCTOR ALLOY FIN FIELD EFFECT TRANSISTOR Aug 21, 2014 Abandoned
Array ( [id] => 10397308 [patent_doc_number] => 20150282315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/339618 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3784 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14339618 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/339618
PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME Jul 23, 2014 Abandoned
Array ( [id] => 10674101 [patent_doc_number] => 20160020246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'METHOD FOR FABRICATING CMOS IMAGE SENSORS AND SURFACE TREATING PROCESS THEREOF' [patent_app_type] => utility [patent_app_number] => 14/332346 [patent_app_country] => US [patent_app_date] => 2014-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14332346 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/332346
METHOD FOR FABRICATING CMOS IMAGE SENSORS AND SURFACE TREATING PROCESS THEREOF Jul 14, 2014 Abandoned
Array ( [id] => 10495236 [patent_doc_number] => 20150380258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'METHOD FOR CONTROLLING HEIGHT OF A FIN STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/314384 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6300 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14314384 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/314384
METHOD FOR CONTROLLING HEIGHT OF A FIN STRUCTURE Jun 24, 2014 Abandoned
Array ( [id] => 10486896 [patent_doc_number] => 20150371916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'PRE-APPLIED UNDERFILL' [patent_app_type] => utility [patent_app_number] => 14/312682 [patent_app_country] => US [patent_app_date] => 2014-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11170 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14312682 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/312682
PRE-APPLIED UNDERFILL Jun 22, 2014 Abandoned
Array ( [id] => 10378033 [patent_doc_number] => 20150263040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same' [patent_app_type] => utility [patent_app_number] => 14/216553 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14216553 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/216553
Embedded Memory Device With Silicon-On-Insulator Substrate, And Method Of Making Same Mar 16, 2014 Abandoned
Array ( [id] => 10370425 [patent_doc_number] => 20150255430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/201934 [patent_app_country] => US [patent_app_date] => 2014-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3051 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14201934 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/201934
PACKAGE STRUCTURE Mar 9, 2014 Abandoned
Array ( [id] => 9585320 [patent_doc_number] => 08775328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-08 [patent_title] => 'Geo-spatially constrained private neighborhood social network' [patent_app_type] => utility [patent_app_number] => 14/203531 [patent_app_country] => US [patent_app_date] => 2014-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 44 [patent_no_of_words] => 39407 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14203531 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/203531
Geo-spatially constrained private neighborhood social network Mar 9, 2014 Issued
Array ( [id] => 9499707 [patent_doc_number] => 08738545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Map based neighborhood search and community contribution' [patent_app_type] => utility [patent_app_number] => 14/144612 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 47469 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144612 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/144612
Map based neighborhood search and community contribution Dec 30, 2013 Issued
Array ( [id] => 10847293 [patent_doc_number] => 08874489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Short-term residential spaces in a geo-spatial environment' [patent_app_type] => utility [patent_app_number] => 14/102474 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 48114 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14102474 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/102474
Short-term residential spaces in a geo-spatial environment Dec 9, 2013 Issued
Menu