Craig S. Goldschmidt

Array ( [id] => 14234921 [patent_doc_number] => 20190129633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => INITIALISATION OF A STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/798259 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14234925 [patent_doc_number] => 20190129635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/798083 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16706143 [patent_doc_number] => 10956074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Data storage method, memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 15/798370 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10182 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12665395 [patent_doc_number] => 20180113631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => ENHANCING FLASH TRANSLATION LAYER TO IMPROVE PERFORMANCE OF DATABASES AND FILESYSTEMS [patent_app_type] => utility [patent_app_number] => 15/726839 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15638873 [patent_doc_number] => 10592430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Memory structure comprising scratchpad memory [patent_app_type] => utility [patent_app_number] => 15/726749 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 12238 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14162059 [patent_doc_number] => 20190108132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => ADDRESS TRANSLATION FOR SENDING REAL ADDRESS TO MEMORY SUBSYSTEM IN EFFECTIVE ADDRESS BASED LOAD-STORE UNIT [patent_app_type] => utility [patent_app_number] => 15/726650 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17136572 [patent_doc_number] => 11138125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Hybrid cache memory and method for reducing latency in the same [patent_app_type] => utility [patent_app_number] => 15/701575 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5483 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12221869 [patent_doc_number] => 20180060229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'TECHNIQUES FOR IMPLEMENTING MEMORY SEGMENTATION IN A WELDING OR CUTTING SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/687493 [patent_app_country] => US [patent_app_date] => 2017-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12713338 [patent_doc_number] => 20180129612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => DETECTION OF AVOIDABLE CACHE THRASHING FOR OLTP AND DW WORKLOADS [patent_app_type] => utility [patent_app_number] => 15/687296 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15058717 [patent_doc_number] => 10459661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Stream identifier based storage system for managing an array of SSDs [patent_app_type] => utility [patent_app_number] => 15/687167 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12004162 [patent_doc_number] => 20170308316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'VIRTUAL STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/646364 [patent_app_country] => US [patent_app_date] => 2017-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 27035 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15646364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12004147 [patent_doc_number] => 20170308302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'STORAGE MANAGEMENT IN HYBRID DRIVES' [patent_app_type] => utility [patent_app_number] => 15/625944 [patent_app_country] => US [patent_app_date] => 2017-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9954 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15625944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14298837 [patent_doc_number] => 10289545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Hybrid checkpointed memory [patent_app_type] => utility [patent_app_number] => 15/610577 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 27919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15610577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13483277 [patent_doc_number] => 20180293181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => SECURED CHIP ENABLE WITH CHIP DISABLE [patent_app_type] => utility [patent_app_number] => 15/484986 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15484986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13482897 [patent_doc_number] => 20180292991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => MEMORY PROTOCOL WITH PROGRAMMABLE BUFFER AND CACHE SIZE [patent_app_type] => utility [patent_app_number] => 15/484793 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15484793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15197597 [patent_doc_number] => 10496290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-03 [patent_title] => Method and system for window-based churn handling in data cache [patent_app_type] => utility [patent_app_number] => 15/485033 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8217 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11759287 [patent_doc_number] => 20170206157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'RECOVERY FOR NON-VOLATILE MEMORY AFTER POWER LOSS' [patent_app_type] => utility [patent_app_number] => 15/477169 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6431 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15501189 [patent_doc_number] => 20200050783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => INFORMATION PROCESSING DEVICE AND COMPUTER READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/475460 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16475460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14426785 [patent_doc_number] => 10318196 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-11 [patent_title] => Stateless storage system controller in a direct flash storage system [patent_app_type] => utility [patent_app_number] => 15/414760 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6506 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11717022 [patent_doc_number] => 20170185521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'SEMICONDUCTOR DEVICE, DATA PROCESSING SYSTEM, AND SEMICONDUCTOR DEVICE CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 15/358133 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6467 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15358133 [rel_patent_id] =>[rel_patent_doc_number] =>)