Search

Craig Thompson

Examiner (ID: 2411)

Most Active Art Unit
2813
Art Unit(s)
2811, 2812, 2813, 3999
Total Applications
616
Issued Applications
589
Pending Applications
10
Abandoned Applications
17

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 988359 [patent_doc_number] => 06921914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'Process for producing semiconductor article using graded epitaxial growth' [patent_app_type] => utility [patent_app_number] => 10/802185 [patent_app_country] => US [patent_app_date] => 2004-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4170 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/921/06921914.pdf [firstpage_image] =>[orig_patent_app_number] => 10802185 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/802185
Process for producing semiconductor article using graded epitaxial growth Mar 16, 2004 Issued
Array ( [id] => 1047280 [patent_doc_number] => 06864524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Hybrid bulk/silicon-on-insulator multiprocessors' [patent_app_type] => utility [patent_app_number] => 10/786276 [patent_app_country] => US [patent_app_date] => 2004-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7013 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864524.pdf [firstpage_image] =>[orig_patent_app_number] => 10786276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/786276
Hybrid bulk/silicon-on-insulator multiprocessors Feb 23, 2004 Issued
Array ( [id] => 1031530 [patent_doc_number] => 06879044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Structure for contact formation using a silicon-germanium alloy' [patent_app_type] => utility [patent_app_number] => 10/782685 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5776 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/879/06879044.pdf [firstpage_image] =>[orig_patent_app_number] => 10782685 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/782685
Structure for contact formation using a silicon-germanium alloy Feb 18, 2004 Issued
Array ( [id] => 7465691 [patent_doc_number] => 20040166673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Scaffold-organized clusters and electronic devices made using such clusters' [patent_app_type] => new [patent_app_number] => 10/783515 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 18462 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20040166673.pdf [firstpage_image] =>[orig_patent_app_number] => 10783515 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/783515
Scaffold-organized clusters and electronic made using such clusters Feb 18, 2004 Issued
Array ( [id] => 7429066 [patent_doc_number] => 20040161874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Method of forming a non-volatile resistance variable device, and non-volatile resistance variable device' [patent_app_type] => new [patent_app_number] => 10/777755 [patent_app_country] => US [patent_app_date] => 2004-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3024 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20040161874.pdf [firstpage_image] =>[orig_patent_app_number] => 10777755 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/777755
Method of forming a non-volatile resistance variable device Feb 12, 2004 Issued
Array ( [id] => 7429105 [patent_doc_number] => 20040161877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Wafer cutting using laser marking' [patent_app_type] => new [patent_app_number] => 10/777619 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4158 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20040161877.pdf [firstpage_image] =>[orig_patent_app_number] => 10777619 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/777619
Wafer cutting using laser marking Feb 11, 2004 Issued
Array ( [id] => 1065557 [patent_doc_number] => 06846709 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-25 [patent_title] => 'Vertical gate CMOS with lithography-independent gate length' [patent_app_type] => utility [patent_app_number] => 10/761876 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 3258 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/846/06846709.pdf [firstpage_image] =>[orig_patent_app_number] => 10761876 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761876
Vertical gate CMOS with lithography-independent gate length Jan 20, 2004 Issued
Array ( [id] => 1040539 [patent_doc_number] => 06869837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-22 [patent_title] => 'Methods of fabricating a word-line spacer for wide over-etching window on outside diameter (OD) and strong fence' [patent_app_type] => utility [patent_app_number] => 10/758316 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2158 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/869/06869837.pdf [firstpage_image] =>[orig_patent_app_number] => 10758316 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/758316
Methods of fabricating a word-line spacer for wide over-etching window on outside diameter (OD) and strong fence Jan 14, 2004 Issued
Array ( [id] => 1037521 [patent_doc_number] => 06872670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Silylation treatment unit and method' [patent_app_type] => utility [patent_app_number] => 10/752556 [patent_app_country] => US [patent_app_date] => 2004-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 7266 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872670.pdf [firstpage_image] =>[orig_patent_app_number] => 10752556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/752556
Silylation treatment unit and method Jan 7, 2004 Issued
Array ( [id] => 782770 [patent_doc_number] => 06992018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Chemical fluid deposition for the formation of metal and metal alloy films on patterned and unpatterned substrates' [patent_app_type] => utility [patent_app_number] => 10/745843 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 17130 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/992/06992018.pdf [firstpage_image] =>[orig_patent_app_number] => 10745843 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/745843
Chemical fluid deposition for the formation of metal and metal alloy films on patterned and unpatterned substrates Dec 23, 2003 Issued
Array ( [id] => 1112901 [patent_doc_number] => 06803277 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Method of forming gate electrode in flash memory device' [patent_app_type] => B1 [patent_app_number] => 10/744495 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3163 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/803/06803277.pdf [firstpage_image] =>[orig_patent_app_number] => 10744495 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744495
Method of forming gate electrode in flash memory device Dec 22, 2003 Issued
Array ( [id] => 1062759 [patent_doc_number] => 06849503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Method for forming metal interconnections for flash memory device' [patent_app_type] => utility [patent_app_number] => 10/744426 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2537 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849503.pdf [firstpage_image] =>[orig_patent_app_number] => 10744426 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744426
Method for forming metal interconnections for flash memory device Dec 21, 2003 Issued
Array ( [id] => 7429674 [patent_doc_number] => 20040266133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Method for manufacturing shallow trench isolation in semiconductor device' [patent_app_type] => new [patent_app_number] => 10/735913 [patent_app_country] => US [patent_app_date] => 2003-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3620 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266133.pdf [firstpage_image] =>[orig_patent_app_number] => 10735913 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/735913
Method for manufacturing shallow trench isolation in semiconductor device Dec 15, 2003 Issued
Array ( [id] => 931098 [patent_doc_number] => 06979602 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-27 [patent_title] => 'Method for making a recessed thyristor control port' [patent_app_type] => utility [patent_app_number] => 10/730755 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4534 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979602.pdf [firstpage_image] =>[orig_patent_app_number] => 10730755 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/730755
Method for making a recessed thyristor control port Dec 7, 2003 Issued
Array ( [id] => 1017976 [patent_doc_number] => 06890870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Method for controlling electrical conductivity' [patent_app_type] => utility [patent_app_number] => 10/715446 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4039 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/890/06890870.pdf [firstpage_image] =>[orig_patent_app_number] => 10715446 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/715446
Method for controlling electrical conductivity Nov 18, 2003 Issued
Array ( [id] => 7122514 [patent_doc_number] => 20050014343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Method for fabricating capacitor in semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/705096 [patent_app_country] => US [patent_app_date] => 2003-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2634 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20050014343.pdf [firstpage_image] =>[orig_patent_app_number] => 10705096 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/705096
Method for fabricating capacitor in semiconductor device Nov 9, 2003 Issued
Array ( [id] => 1134268 [patent_doc_number] => 06784073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-31 [patent_title] => 'Method of making semiconductor-on-insulator device with thermoelectric cooler' [patent_app_type] => B1 [patent_app_number] => 10/704508 [patent_app_country] => US [patent_app_date] => 2003-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 3847 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784073.pdf [firstpage_image] =>[orig_patent_app_number] => 10704508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/704508
Method of making semiconductor-on-insulator device with thermoelectric cooler Nov 6, 2003 Issued
Array ( [id] => 7353641 [patent_doc_number] => 20040089896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Semiconductor device having high breakdown voltage without increased on resistance' [patent_app_type] => new [patent_app_number] => 10/695811 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4027 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20040089896.pdf [firstpage_image] =>[orig_patent_app_number] => 10695811 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695811
Semiconductor device having high breakdown voltage without increased on resistance Oct 29, 2003 Issued
Array ( [id] => 964967 [patent_doc_number] => 06950362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/686826 [patent_app_country] => US [patent_app_date] => 2003-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 8227 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950362.pdf [firstpage_image] =>[orig_patent_app_number] => 10686826 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/686826
Semiconductor memory device Oct 14, 2003 Issued
Array ( [id] => 1017886 [patent_doc_number] => 06890780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Method for forming an electrostatically-doped carbon nanotube device' [patent_app_type] => utility [patent_app_number] => 10/683895 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3744 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/890/06890780.pdf [firstpage_image] =>[orig_patent_app_number] => 10683895 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/683895
Method for forming an electrostatically-doped carbon nanotube device Oct 9, 2003 Issued
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