Search

Craig Thompson

Examiner (ID: 2411)

Most Active Art Unit
2813
Art Unit(s)
2811, 2812, 2813, 3999
Total Applications
616
Issued Applications
589
Pending Applications
10
Abandoned Applications
17

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4274558 [patent_doc_number] => 06281022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Multi-phase lead germanate film deposition method' [patent_app_type] => 1 [patent_app_number] => 9/704496 [patent_app_country] => US [patent_app_date] => 2000-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 6345 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281022.pdf [firstpage_image] =>[orig_patent_app_number] => 704496 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/704496
Multi-phase lead germanate film deposition method Oct 31, 2000 Issued
Array ( [id] => 4357884 [patent_doc_number] => 06255146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Thin film transistor and a method of manufacturing thereof' [patent_app_type] => 1 [patent_app_number] => 9/699461 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 84 [patent_no_of_words] => 10564 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255146.pdf [firstpage_image] =>[orig_patent_app_number] => 699461 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/699461
Thin film transistor and a method of manufacturing thereof Oct 30, 2000 Issued
Array ( [id] => 4267812 [patent_doc_number] => 06306780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method for making a photoresist layer having increased resistance to blistering, peeling, lifting, or reticulation' [patent_app_type] => 1 [patent_app_number] => 9/698375 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2875 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306780.pdf [firstpage_image] =>[orig_patent_app_number] => 698375 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/698375
Method for making a photoresist layer having increased resistance to blistering, peeling, lifting, or reticulation Oct 25, 2000 Issued
Array ( [id] => 1594199 [patent_doc_number] => 06383826 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method for determining etch depth' [patent_app_type] => B1 [patent_app_number] => 09/691636 [patent_app_country] => US [patent_app_date] => 2000-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1108 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383826.pdf [firstpage_image] =>[orig_patent_app_number] => 09691636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/691636
Method for determining etch depth Oct 17, 2000 Issued
Array ( [id] => 4344298 [patent_doc_number] => 06284620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components' [patent_app_type] => 1 [patent_app_number] => 9/688466 [patent_app_country] => US [patent_app_date] => 2000-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1990 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284620.pdf [firstpage_image] =>[orig_patent_app_number] => 688466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/688466
Method for fabricating an SOI wafer for low-impedance high-voltage semiconductor components Oct 15, 2000 Issued
Array ( [id] => 4301378 [patent_doc_number] => 06251697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Non-contact method for monitoring and controlling plasma charging damage in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/684015 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3067 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251697.pdf [firstpage_image] =>[orig_patent_app_number] => 684015 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/684015
Non-contact method for monitoring and controlling plasma charging damage in a semiconductor device Oct 5, 2000 Issued
Array ( [id] => 1513519 [patent_doc_number] => 06442736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Semiconductor processing system and method for controlling moisture level therein' [patent_app_type] => B1 [patent_app_number] => 09/677885 [patent_app_country] => US [patent_app_date] => 2000-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6182 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442736.pdf [firstpage_image] =>[orig_patent_app_number] => 09677885 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677885
Semiconductor processing system and method for controlling moisture level therein Oct 2, 2000 Issued
Array ( [id] => 4380546 [patent_doc_number] => 06277661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method for detecting sloped contact holes using a critical-dimension waveform' [patent_app_type] => 1 [patent_app_number] => 9/677955 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2600 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277661.pdf [firstpage_image] =>[orig_patent_app_number] => 677955 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677955
Method for detecting sloped contact holes using a critical-dimension waveform Oct 1, 2000 Issued
Array ( [id] => 4270517 [patent_doc_number] => 06323050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method for evaluating decoupling capacitor placement for VLSI chips' [patent_app_type] => 1 [patent_app_number] => 9/677285 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3458 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323050.pdf [firstpage_image] =>[orig_patent_app_number] => 677285 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677285
Method for evaluating decoupling capacitor placement for VLSI chips Oct 1, 2000 Issued
Array ( [id] => 4368205 [patent_doc_number] => 06287883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method for fabricating LED' [patent_app_type] => 1 [patent_app_number] => 9/666606 [patent_app_country] => US [patent_app_date] => 2000-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 1765 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287883.pdf [firstpage_image] =>[orig_patent_app_number] => 666606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/666606
Method for fabricating LED Sep 19, 2000 Issued
Array ( [id] => 4368099 [patent_doc_number] => 06287876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Reticle-substrate alignment methods for charged-particle-beam microlithography, and associated semiconductor-device manufacturing methods' [patent_app_type] => 1 [patent_app_number] => 9/656406 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6148 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287876.pdf [firstpage_image] =>[orig_patent_app_number] => 656406 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/656406
Reticle-substrate alignment methods for charged-particle-beam microlithography, and associated semiconductor-device manufacturing methods Sep 5, 2000 Issued
Array ( [id] => 4275585 [patent_doc_number] => 06281091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Container capacitor structure and method of formation thereof' [patent_app_type] => 1 [patent_app_number] => 9/653000 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 6991 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281091.pdf [firstpage_image] =>[orig_patent_app_number] => 653000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653000
Container capacitor structure and method of formation thereof Aug 30, 2000 Issued
Array ( [id] => 4324970 [patent_doc_number] => 06329263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method of forming a container capacitor structure' [patent_app_type] => 1 [patent_app_number] => 9/653259 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 6997 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329263.pdf [firstpage_image] =>[orig_patent_app_number] => 653259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653259
Method of forming a container capacitor structure Aug 30, 2000 Issued
Array ( [id] => 4318318 [patent_doc_number] => 06248608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Manufacturing method of a gallium nitride-based blue light emitting diode (LED) ohmic electrodes' [patent_app_type] => 1 [patent_app_number] => 9/653496 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1525 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248608.pdf [firstpage_image] =>[orig_patent_app_number] => 653496 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653496
Manufacturing method of a gallium nitride-based blue light emitting diode (LED) ohmic electrodes Aug 30, 2000 Issued
Array ( [id] => 4407844 [patent_doc_number] => 06300158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Integrated solar power module' [patent_app_type] => 1 [patent_app_number] => 9/649726 [patent_app_country] => US [patent_app_date] => 2000-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3691 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300158.pdf [firstpage_image] =>[orig_patent_app_number] => 649726 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/649726
Integrated solar power module Aug 27, 2000 Issued
Array ( [id] => 1469846 [patent_doc_number] => 06406980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets' [patent_app_type] => B1 [patent_app_number] => 09/645155 [patent_app_country] => US [patent_app_date] => 2000-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2645 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/406/06406980.pdf [firstpage_image] =>[orig_patent_app_number] => 09645155 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/645155
Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets Aug 23, 2000 Issued
09/645036 PROCESS FOR PRODUCING A SEMICONDUCTOR DEVICE Aug 23, 2000 Abandoned
Array ( [id] => 4380679 [patent_doc_number] => 06294393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Reduction of imprint in ferroelectric devices using a depoling technique' [patent_app_type] => 1 [patent_app_number] => 9/644222 [patent_app_country] => US [patent_app_date] => 2000-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1757 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294393.pdf [firstpage_image] =>[orig_patent_app_number] => 644222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/644222
Reduction of imprint in ferroelectric devices using a depoling technique Aug 22, 2000 Issued
Array ( [id] => 4310488 [patent_doc_number] => 06316334 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array' [patent_app_type] => 1 [patent_app_number] => 9/642394 [patent_app_country] => US [patent_app_date] => 2000-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 1836 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316334.pdf [firstpage_image] =>[orig_patent_app_number] => 642394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642394
Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array Aug 17, 2000 Issued
Array ( [id] => 1570151 [patent_doc_number] => 06498049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Display devices' [patent_app_type] => B1 [patent_app_number] => 09/640436 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4650 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498049.pdf [firstpage_image] =>[orig_patent_app_number] => 09640436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/640436
Display devices Aug 16, 2000 Issued
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