
Craig Thompson
Examiner (ID: 14661)
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2811, 2813, 2812, 3999 |
| Total Applications | 616 |
| Issued Applications | 589 |
| Pending Applications | 10 |
| Abandoned Applications | 17 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7383633
[patent_doc_number] => 20040082189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-29
[patent_title] => 'Multi-layer circuit board and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/680116
[patent_app_country] => US
[patent_app_date] => 2003-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3558
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20040082189.pdf
[firstpage_image] =>[orig_patent_app_number] => 10680116
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/680116 | Multi-layer circuit board and method of manufacturing the same | Oct 7, 2003 | Issued |
Array
(
[id] => 7434212
[patent_doc_number] => 20040049899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-18
[patent_title] => 'Method of manufacturing solid-state electrolytic capacitor'
[patent_app_type] => new
[patent_app_number] => 10/415946
[patent_app_country] => US
[patent_app_date] => 2003-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5154
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 248
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20040049899.pdf
[firstpage_image] =>[orig_patent_app_number] => 10415946
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/415946 | Method of manufacturing solid-state electrolytic capacitor | Oct 7, 2003 | Issued |
Array
(
[id] => 963593
[patent_doc_number] => 06949405
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-27
[patent_title] => 'Method for producing channels and cavities in semiconductor housings, and an electronic component having such channels and cavities'
[patent_app_type] => utility
[patent_app_number] => 10/679086
[patent_app_country] => US
[patent_app_date] => 2003-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5049
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/949/06949405.pdf
[firstpage_image] =>[orig_patent_app_number] => 10679086
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/679086 | Method for producing channels and cavities in semiconductor housings, and an electronic component having such channels and cavities | Oct 1, 2003 | Issued |
Array
(
[id] => 7167174
[patent_doc_number] => 20040077125
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-22
[patent_title] => 'Method of transferring semiconductor chips'
[patent_app_type] => new
[patent_app_number] => 10/677606
[patent_app_country] => US
[patent_app_date] => 2003-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2292
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20040077125.pdf
[firstpage_image] =>[orig_patent_app_number] => 10677606
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/677606 | Method of transferring semiconductor chips | Oct 1, 2003 | Issued |
Array
(
[id] => 1146471
[patent_doc_number] => 06774008
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-08-10
[patent_title] => 'Method for fabricating shallow trench isolation between deep trench capacitors'
[patent_app_type] => B1
[patent_app_number] => 10/605076
[patent_app_country] => US
[patent_app_date] => 2003-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 1967
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/774/06774008.pdf
[firstpage_image] =>[orig_patent_app_number] => 10605076
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/605076 | Method for fabricating shallow trench isolation between deep trench capacitors | Sep 6, 2003 | Issued |
Array
(
[id] => 1065552
[patent_doc_number] => 06846706
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-25
[patent_title] => 'Power MOSFET with ultra-deep base and reduced on resistance'
[patent_app_type] => utility
[patent_app_number] => 10/644306
[patent_app_country] => US
[patent_app_date] => 2003-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 23
[patent_no_of_words] => 3571
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/846/06846706.pdf
[firstpage_image] =>[orig_patent_app_number] => 10644306
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/644306 | Power MOSFET with ultra-deep base and reduced on resistance | Aug 19, 2003 | Issued |
Array
(
[id] => 7344035
[patent_doc_number] => 20040191968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => '[METHOD OF FABRICATING A THIN FILM TRANSISTOR ARRAY PANELSUBSTRATE]'
[patent_app_type] => new
[patent_app_number] => 10/604806
[patent_app_country] => US
[patent_app_date] => 2003-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5231
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20040191968.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604806
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604806 | Method of fabricating a thin film transistor array panelsubstrate | Aug 18, 2003 | Issued |
Array
(
[id] => 6971848
[patent_doc_number] => 20050037558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Method for fabricating transistor having fully silicided gate'
[patent_app_type] => utility
[patent_app_number] => 10/643675
[patent_app_country] => US
[patent_app_date] => 2003-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1673
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20050037558.pdf
[firstpage_image] =>[orig_patent_app_number] => 10643675
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/643675 | Method for fabricating transistor having fully silicided gate | Aug 14, 2003 | Issued |
Array
(
[id] => 1027885
[patent_doc_number] => 06881600
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-19
[patent_title] => 'Etching in combination with other processing techniques to facilitate alignment of a die in a system and structures formed thereby'
[patent_app_type] => utility
[patent_app_number] => 10/628575
[patent_app_country] => US
[patent_app_date] => 2003-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 21
[patent_no_of_words] => 2682
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/881/06881600.pdf
[firstpage_image] =>[orig_patent_app_number] => 10628575
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/628575 | Etching in combination with other processing techniques to facilitate alignment of a die in a system and structures formed thereby | Jul 28, 2003 | Issued |
Array
(
[id] => 7260216
[patent_doc_number] => 20040150060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-05
[patent_title] => 'Semiconductor device and method of manufacturing same'
[patent_app_type] => new
[patent_app_number] => 10/626656
[patent_app_country] => US
[patent_app_date] => 2003-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6920
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0150/20040150060.pdf
[firstpage_image] =>[orig_patent_app_number] => 10626656
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/626656 | Semiconductor device and method of manufacturing same | Jul 24, 2003 | Issued |
Array
(
[id] => 1080453
[patent_doc_number] => 06835611
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-12-28
[patent_title] => 'Structure of metal oxide semiconductor field effect transistor'
[patent_app_type] => B1
[patent_app_number] => 10/625516
[patent_app_country] => US
[patent_app_date] => 2003-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 1758
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/835/06835611.pdf
[firstpage_image] =>[orig_patent_app_number] => 10625516
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/625516 | Structure of metal oxide semiconductor field effect transistor | Jul 23, 2003 | Issued |
Array
(
[id] => 7297308
[patent_doc_number] => 20040125265
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'Crystallization method of silicon thin film, thin film transistor manufactured using the method, and flat panel display including the thin film transistor'
[patent_app_type] => new
[patent_app_number] => 10/624636
[patent_app_country] => US
[patent_app_date] => 2003-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7105
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0125/20040125265.pdf
[firstpage_image] =>[orig_patent_app_number] => 10624636
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/624636 | Crystallization method of silicon thin film, thin film transistor manufactured using the method, and flat panel display including the thin film transistor | Jul 22, 2003 | Issued |
Array
(
[id] => 7675123
[patent_doc_number] => 20040126995
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'Method for forming scribed groove and scribing apparatus'
[patent_app_type] => new
[patent_app_number] => 10/624985
[patent_app_country] => US
[patent_app_date] => 2003-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7125
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0126/20040126995.pdf
[firstpage_image] =>[orig_patent_app_number] => 10624985
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/624985 | Method for forming scribed groove and scribing apparatus | Jul 21, 2003 | Issued |
Array
(
[id] => 7398682
[patent_doc_number] => 20040018653
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'Method of measuring meso-scale structures on wafers'
[patent_app_type] => new
[patent_app_number] => 10/621218
[patent_app_country] => US
[patent_app_date] => 2003-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 12821
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20040018653.pdf
[firstpage_image] =>[orig_patent_app_number] => 10621218
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/621218 | Method of measuring meso-scale structures on wafers | Jul 15, 2003 | Issued |
Array
(
[id] => 1063657
[patent_doc_number] => 06849900
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-01
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/606755
[patent_app_country] => US
[patent_app_date] => 2003-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3496
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/849/06849900.pdf
[firstpage_image] =>[orig_patent_app_number] => 10606755
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/606755 | Semiconductor device | Jun 26, 2003 | Issued |
Array
(
[id] => 7626581
[patent_doc_number] => 06768181
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-27
[patent_title] => 'Micro-machined electromechanical sensors (MEMS) devices'
[patent_app_type] => B2
[patent_app_number] => 10/461036
[patent_app_country] => US
[patent_app_date] => 2003-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3751
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 8
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/768/06768181.pdf
[firstpage_image] =>[orig_patent_app_number] => 10461036
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/461036 | Micro-machined electromechanical sensors (MEMS) devices | Jun 12, 2003 | Issued |
Array
(
[id] => 7278803
[patent_doc_number] => 20040061180
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-01
[patent_title] => '1T1R resistive memory'
[patent_app_type] => new
[patent_app_number] => 10/453156
[patent_app_country] => US
[patent_app_date] => 2003-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2247
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0061/20040061180.pdf
[firstpage_image] =>[orig_patent_app_number] => 10453156
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/453156 | 1T1R resistive memory | Jun 2, 2003 | Issued |
Array
(
[id] => 6807337
[patent_doc_number] => 20030197276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-23
[patent_title] => 'Damascene resistor and method for measuring the width of same'
[patent_app_type] => new
[patent_app_number] => 10/447646
[patent_app_country] => US
[patent_app_date] => 2003-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3727
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20030197276.pdf
[firstpage_image] =>[orig_patent_app_number] => 10447646
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/447646 | Damascene resistor and method for measuring the width of same | May 28, 2003 | Issued |
Array
(
[id] => 1123375
[patent_doc_number] => 06794254
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-09-21
[patent_title] => 'Embedded dual-port DRAM process'
[patent_app_type] => B1
[patent_app_number] => 10/438646
[patent_app_country] => US
[patent_app_date] => 2003-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 19
[patent_no_of_words] => 4588
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/794/06794254.pdf
[firstpage_image] =>[orig_patent_app_number] => 10438646
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/438646 | Embedded dual-port DRAM process | May 14, 2003 | Issued |
Array
(
[id] => 1062740
[patent_doc_number] => 06849484
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-01
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/435046
[patent_app_country] => US
[patent_app_date] => 2003-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 51
[patent_no_of_words] => 5501
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/849/06849484.pdf
[firstpage_image] =>[orig_patent_app_number] => 10435046
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/435046 | Method of manufacturing semiconductor device | May 11, 2003 | Issued |