Search

Craig Thompson

Examiner (ID: 2411)

Most Active Art Unit
2813
Art Unit(s)
2811, 2812, 2813, 3999
Total Applications
616
Issued Applications
589
Pending Applications
10
Abandoned Applications
17

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4030560 [patent_doc_number] => 05963779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Integrated circuit using a back gate voltage for burn-in operations' [patent_app_type] => 1 [patent_app_number] => 9/211606 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3465 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963779.pdf [firstpage_image] =>[orig_patent_app_number] => 211606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/211606
Integrated circuit using a back gate voltage for burn-in operations Dec 14, 1998 Issued
Array ( [id] => 4235352 [patent_doc_number] => 06143601 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method of fabricating DRAM' [patent_app_type] => 1 [patent_app_number] => 9/208714 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2146 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143601.pdf [firstpage_image] =>[orig_patent_app_number] => 208714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208714
Method of fabricating DRAM Dec 8, 1998 Issued
Array ( [id] => 4139363 [patent_doc_number] => 06060368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Mask pattern correction method' [patent_app_type] => 1 [patent_app_number] => 9/206364 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 4345 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060368.pdf [firstpage_image] =>[orig_patent_app_number] => 206364 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206364
Mask pattern correction method Dec 6, 1998 Issued
Array ( [id] => 4250006 [patent_doc_number] => 06207522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Formation of thin film capacitors' [patent_app_type] => 1 [patent_app_number] => 9/198285 [patent_app_country] => US [patent_app_date] => 1998-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 20899 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207522.pdf [firstpage_image] =>[orig_patent_app_number] => 198285 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/198285
Formation of thin film capacitors Nov 22, 1998 Issued
Array ( [id] => 4136650 [patent_doc_number] => 06015744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Method of manufacturing a shallow trench isolation alignment mark' [patent_app_type] => 1 [patent_app_number] => 9/186544 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 1960 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/015/06015744.pdf [firstpage_image] =>[orig_patent_app_number] => 186544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186544
Method of manufacturing a shallow trench isolation alignment mark Nov 4, 1998 Issued
Array ( [id] => 4353577 [patent_doc_number] => 06218233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Thin film capacitor having an improved bottom electrode and method of forming the same' [patent_app_type] => 1 [patent_app_number] => 9/185586 [patent_app_country] => US [patent_app_date] => 1998-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12054 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218233.pdf [firstpage_image] =>[orig_patent_app_number] => 185586 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185586
Thin film capacitor having an improved bottom electrode and method of forming the same Nov 3, 1998 Issued
Array ( [id] => 4219008 [patent_doc_number] => 06040226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Method for fabricating a thin film inductor' [patent_app_type] => 1 [patent_app_number] => 9/177908 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5291 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040226.pdf [firstpage_image] =>[orig_patent_app_number] => 177908 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/177908
Method for fabricating a thin film inductor Oct 22, 1998 Issued
Array ( [id] => 4219046 [patent_doc_number] => 06040229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Method for manufacturing a solid electrolytic capacitor array' [patent_app_type] => 1 [patent_app_number] => 9/175786 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 90 [patent_no_of_words] => 7479 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040229.pdf [firstpage_image] =>[orig_patent_app_number] => 175786 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175786
Method for manufacturing a solid electrolytic capacitor array Oct 19, 1998 Issued
Array ( [id] => 4286147 [patent_doc_number] => 06211031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method to produce dual polysilicon resistance in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/165000 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1418 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211031.pdf [firstpage_image] =>[orig_patent_app_number] => 165000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/165000
Method to produce dual polysilicon resistance in an integrated circuit Sep 30, 1998 Issued
Array ( [id] => 4085187 [patent_doc_number] => 06017770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Method of making a hybrid micro-electromagnetic article of manufacture' [patent_app_type] => 1 [patent_app_number] => 9/164524 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2732 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/017/06017770.pdf [firstpage_image] =>[orig_patent_app_number] => 164524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164524
Method of making a hybrid micro-electromagnetic article of manufacture Sep 29, 1998 Issued
Array ( [id] => 4087147 [patent_doc_number] => 06133111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method of making photo alignment structure' [patent_app_type] => 1 [patent_app_number] => 9/164167 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 30 [patent_no_of_words] => 3742 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133111.pdf [firstpage_image] =>[orig_patent_app_number] => 164167 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164167
Method of making photo alignment structure Sep 29, 1998 Issued
Array ( [id] => 4411885 [patent_doc_number] => 06193813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Utilization of SiH4 soak and purge in deposition processes' [patent_app_type] => 1 [patent_app_number] => 9/162336 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5817 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/193/06193813.pdf [firstpage_image] =>[orig_patent_app_number] => 162336 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162336
Utilization of SiH4 soak and purge in deposition processes Sep 27, 1998 Issued
Array ( [id] => 4217645 [patent_doc_number] => 06134760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Process for manufacturing electric double layer capacitor' [patent_app_type] => 1 [patent_app_number] => 9/158376 [patent_app_country] => US [patent_app_date] => 1998-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4729 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134760.pdf [firstpage_image] =>[orig_patent_app_number] => 158376 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158376
Process for manufacturing electric double layer capacitor Sep 21, 1998 Issued
Array ( [id] => 4151951 [patent_doc_number] => 06124164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method of making integrated capacitor incorporating high K dielectric' [patent_app_type] => 1 [patent_app_number] => 9/156545 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124164.pdf [firstpage_image] =>[orig_patent_app_number] => 156545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156545
Method of making integrated capacitor incorporating high K dielectric Sep 16, 1998 Issued
Array ( [id] => 4168430 [patent_doc_number] => 06140140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method for detecting process sensitivity to integrated circuit layout by compound processing' [patent_app_type] => 1 [patent_app_number] => 9/154075 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4397 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140140.pdf [firstpage_image] =>[orig_patent_app_number] => 154075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154075
Method for detecting process sensitivity to integrated circuit layout by compound processing Sep 15, 1998 Issued
Array ( [id] => 4420871 [patent_doc_number] => 06225237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method for forming metal-containing films using metal complexes with chelating O- and/or N-donor ligands' [patent_app_type] => 1 [patent_app_number] => 9/144745 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6071 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225237.pdf [firstpage_image] =>[orig_patent_app_number] => 144745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/144745
Method for forming metal-containing films using metal complexes with chelating O- and/or N-donor ligands Aug 31, 1998 Issued
Array ( [id] => 4155696 [patent_doc_number] => 06156604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method for making an open bit line memory cell with a vertical transistor and trench plate trench capacitor' [patent_app_type] => 1 [patent_app_number] => 9/143606 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5511 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156604.pdf [firstpage_image] =>[orig_patent_app_number] => 143606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143606
Method for making an open bit line memory cell with a vertical transistor and trench plate trench capacitor Aug 30, 1998 Issued
Array ( [id] => 4191172 [patent_doc_number] => 06043134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Semiconductor wafer alignment processes' [patent_app_type] => 1 [patent_app_number] => 9/143044 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2434 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043134.pdf [firstpage_image] =>[orig_patent_app_number] => 143044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143044
Semiconductor wafer alignment processes Aug 27, 1998 Issued
Array ( [id] => 4087864 [patent_doc_number] => 06133161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Methods of forming a film on a substrate using complexes having tris(pyrazolyl) methanate ligands' [patent_app_type] => 1 [patent_app_number] => 9/140914 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5677 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133161.pdf [firstpage_image] =>[orig_patent_app_number] => 140914 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140914
Methods of forming a film on a substrate using complexes having tris(pyrazolyl) methanate ligands Aug 26, 1998 Issued
Array ( [id] => 4238054 [patent_doc_number] => 06080625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method for making dual-polysilicon structures in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/140275 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2888 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080625.pdf [firstpage_image] =>[orig_patent_app_number] => 140275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140275
Method for making dual-polysilicon structures in integrated circuits Aug 25, 1998 Issued
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