
Craig Thompson
Examiner (ID: 2411)
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2811, 2812, 2813, 3999 |
| Total Applications | 616 |
| Issued Applications | 589 |
| Pending Applications | 10 |
| Abandoned Applications | 17 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4030560
[patent_doc_number] => 05963779
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Integrated circuit using a back gate voltage for burn-in operations'
[patent_app_type] => 1
[patent_app_number] => 9/211606
[patent_app_country] => US
[patent_app_date] => 1998-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 3465
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/963/05963779.pdf
[firstpage_image] =>[orig_patent_app_number] => 211606
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/211606 | Integrated circuit using a back gate voltage for burn-in operations | Dec 14, 1998 | Issued |
Array
(
[id] => 4235352
[patent_doc_number] => 06143601
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Method of fabricating DRAM'
[patent_app_type] => 1
[patent_app_number] => 9/208714
[patent_app_country] => US
[patent_app_date] => 1998-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[firstpage_image] =>[orig_patent_app_number] => 208714
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/208714 | Method of fabricating DRAM | Dec 8, 1998 | Issued |
Array
(
[id] => 4139363
[patent_doc_number] => 06060368
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Mask pattern correction method'
[patent_app_type] => 1
[patent_app_number] => 9/206364
[patent_app_country] => US
[patent_app_date] => 1998-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/06/060/06060368.pdf
[firstpage_image] =>[orig_patent_app_number] => 206364
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/206364 | Mask pattern correction method | Dec 6, 1998 | Issued |
Array
(
[id] => 4250006
[patent_doc_number] => 06207522
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Formation of thin film capacitors'
[patent_app_type] => 1
[patent_app_number] => 9/198285
[patent_app_country] => US
[patent_app_date] => 1998-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 20899
[patent_no_of_claims] => 11
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[pdf_file] => patents/06/207/06207522.pdf
[firstpage_image] =>[orig_patent_app_number] => 198285
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/198285 | Formation of thin film capacitors | Nov 22, 1998 | Issued |
Array
(
[id] => 4136650
[patent_doc_number] => 06015744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Method of manufacturing a shallow trench isolation alignment mark'
[patent_app_type] => 1
[patent_app_number] => 9/186544
[patent_app_country] => US
[patent_app_date] => 1998-11-05
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[pdf_file] => patents/06/015/06015744.pdf
[firstpage_image] =>[orig_patent_app_number] => 186544
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/186544 | Method of manufacturing a shallow trench isolation alignment mark | Nov 4, 1998 | Issued |
Array
(
[id] => 4353577
[patent_doc_number] => 06218233
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Thin film capacitor having an improved bottom electrode and method of forming the same'
[patent_app_type] => 1
[patent_app_number] => 9/185586
[patent_app_country] => US
[patent_app_date] => 1998-11-04
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[pdf_file] => patents/06/218/06218233.pdf
[firstpage_image] =>[orig_patent_app_number] => 185586
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/185586 | Thin film capacitor having an improved bottom electrode and method of forming the same | Nov 3, 1998 | Issued |
Array
(
[id] => 4219008
[patent_doc_number] => 06040226
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-21
[patent_title] => 'Method for fabricating a thin film inductor'
[patent_app_type] => 1
[patent_app_number] => 9/177908
[patent_app_country] => US
[patent_app_date] => 1998-10-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/040/06040226.pdf
[firstpage_image] =>[orig_patent_app_number] => 177908
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/177908 | Method for fabricating a thin film inductor | Oct 22, 1998 | Issued |
Array
(
[id] => 4219046
[patent_doc_number] => 06040229
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-21
[patent_title] => 'Method for manufacturing a solid electrolytic capacitor array'
[patent_app_type] => 1
[patent_app_number] => 9/175786
[patent_app_country] => US
[patent_app_date] => 1998-10-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/040/06040229.pdf
[firstpage_image] =>[orig_patent_app_number] => 175786
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/175786 | Method for manufacturing a solid electrolytic capacitor array | Oct 19, 1998 | Issued |
Array
(
[id] => 4286147
[patent_doc_number] => 06211031
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Method to produce dual polysilicon resistance in an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/165000
[patent_app_country] => US
[patent_app_date] => 1998-10-01
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[pdf_file] => patents/06/211/06211031.pdf
[firstpage_image] =>[orig_patent_app_number] => 165000
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/165000 | Method to produce dual polysilicon resistance in an integrated circuit | Sep 30, 1998 | Issued |
Array
(
[id] => 4085187
[patent_doc_number] => 06017770
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Method of making a hybrid micro-electromagnetic article of manufacture'
[patent_app_type] => 1
[patent_app_number] => 9/164524
[patent_app_country] => US
[patent_app_date] => 1998-09-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/017/06017770.pdf
[firstpage_image] =>[orig_patent_app_number] => 164524
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164524 | Method of making a hybrid micro-electromagnetic article of manufacture | Sep 29, 1998 | Issued |
Array
(
[id] => 4087147
[patent_doc_number] => 06133111
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-17
[patent_title] => 'Method of making photo alignment structure'
[patent_app_type] => 1
[patent_app_number] => 9/164167
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[pdf_file] => patents/06/133/06133111.pdf
[firstpage_image] =>[orig_patent_app_number] => 164167
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164167 | Method of making photo alignment structure | Sep 29, 1998 | Issued |
Array
(
[id] => 4411885
[patent_doc_number] => 06193813
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Utilization of SiH4 soak and purge in deposition processes'
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[firstpage_image] =>[orig_patent_app_number] => 162336
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Array
(
[id] => 4217645
[patent_doc_number] => 06134760
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Process for manufacturing electric double layer capacitor'
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[patent_app_number] => 9/158376
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[firstpage_image] =>[orig_patent_app_number] => 158376
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/158376 | Process for manufacturing electric double layer capacitor | Sep 21, 1998 | Issued |
Array
(
[id] => 4151951
[patent_doc_number] => 06124164
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[patent_issue_date] => 2000-09-26
[patent_title] => 'Method of making integrated capacitor incorporating high K dielectric'
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[pdf_file] => patents/06/124/06124164.pdf
[firstpage_image] =>[orig_patent_app_number] => 156545
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/156545 | Method of making integrated capacitor incorporating high K dielectric | Sep 16, 1998 | Issued |
Array
(
[id] => 4168430
[patent_doc_number] => 06140140
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[patent_issue_date] => 2000-10-31
[patent_title] => 'Method for detecting process sensitivity to integrated circuit layout by compound processing'
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[firstpage_image] =>[orig_patent_app_number] => 154075
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/154075 | Method for detecting process sensitivity to integrated circuit layout by compound processing | Sep 15, 1998 | Issued |
Array
(
[id] => 4420871
[patent_doc_number] => 06225237
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[patent_title] => 'Method for forming metal-containing films using metal complexes with chelating O- and/or N-donor ligands'
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[pdf_file] => patents/06/225/06225237.pdf
[firstpage_image] =>[orig_patent_app_number] => 144745
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Array
(
[id] => 4155696
[patent_doc_number] => 06156604
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Method for making an open bit line memory cell with a vertical transistor and trench plate trench capacitor'
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[patent_app_number] => 9/143606
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[firstpage_image] =>[orig_patent_app_number] => 143606
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143606 | Method for making an open bit line memory cell with a vertical transistor and trench plate trench capacitor | Aug 30, 1998 | Issued |
Array
(
[id] => 4191172
[patent_doc_number] => 06043134
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143044 | Semiconductor wafer alignment processes | Aug 27, 1998 | Issued |
Array
(
[id] => 4087864
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[firstpage_image] =>[orig_patent_app_number] => 140914
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Array
(
[id] => 4238054
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[pdf_file] => patents/06/080/06080625.pdf
[firstpage_image] =>[orig_patent_app_number] => 140275
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/140275 | Method for making dual-polysilicon structures in integrated circuits | Aug 25, 1998 | Issued |