Craig Thompson

Array ( [id] => 4214567 [patent_doc_number] => 06110792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method for making DRAM capacitor strap' [patent_app_type] => 1 [patent_app_number] => 9/136604 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2196 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110792.pdf [firstpage_image] =>[orig_patent_app_number] => 136604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4233419 [patent_doc_number] => 06074888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method for fabricating semiconductor micro epi-optical components' [patent_app_type] => 1 [patent_app_number] => 9/135696 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2768 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074888.pdf [firstpage_image] =>[orig_patent_app_number] => 135696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4145850 [patent_doc_number] => 06063685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Device level identification methodology' [patent_app_type] => 1 [patent_app_number] => 9/131284 [patent_app_country] => US [patent_app_date] => 1998-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1753 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063685.pdf [firstpage_image] =>[orig_patent_app_number] => 131284 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4101441 [patent_doc_number] => 06100128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Process for making six-transistor SRAM cell local interconnect structure' [patent_app_type] => 1 [patent_app_number] => 9/129254 [patent_app_country] => US [patent_app_date] => 1998-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 4549 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100128.pdf [firstpage_image] =>[orig_patent_app_number] => 129254 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4114020 [patent_doc_number] => 06046094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method of forming wafer alignment patterns' [patent_app_type] => 1 [patent_app_number] => 9/124933 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3917 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046094.pdf [firstpage_image] =>[orig_patent_app_number] => 124933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237589 [patent_doc_number] => 06080593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method of manufacturing ferroelectric memory' [patent_app_type] => 1 [patent_app_number] => 9/123424 [patent_app_country] => US [patent_app_date] => 1998-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1787 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080593.pdf [firstpage_image] =>[orig_patent_app_number] => 123424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4085815 [patent_doc_number] => 06017812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Bump bonding method and bump bonding apparatus' [patent_app_type] => 1 [patent_app_number] => 9/119974 [patent_app_country] => US [patent_app_date] => 1998-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 4892 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/017/06017812.pdf [firstpage_image] =>[orig_patent_app_number] => 119974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4214414 [patent_doc_number] => 06110781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Anisotropic chemical etching process of silicon oxide in the manufacture of MOS transistor flash EPROM devices' [patent_app_type] => 1 [patent_app_number] => 9/115305 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3539 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110781.pdf [firstpage_image] =>[orig_patent_app_number] => 115305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4191194 [patent_doc_number] => 06130123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Method for making a complementary metal gate electrode technology' [patent_app_type] => 1 [patent_app_number] => 9/107604 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4260 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130123.pdf [firstpage_image] =>[orig_patent_app_number] => 107604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4124429 [patent_doc_number] => 06127197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method for measuring width of wire in semiconductor device using measuring-pattern' [patent_app_type] => 1 [patent_app_number] => 9/104716 [patent_app_country] => US [patent_app_date] => 1998-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2093 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127197.pdf [firstpage_image] =>[orig_patent_app_number] => 104716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4093524 [patent_doc_number] => 06099600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method of making a vacuum-treated liquid electrolyte-filled flat electrolytic capacitor' [patent_app_type] => 1 [patent_app_number] => 9/103966 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 59 [patent_no_of_words] => 26739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/099/06099600.pdf [firstpage_image] =>[orig_patent_app_number] => 103966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4031407 [patent_doc_number] => 05907780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Incorporating silicon atoms into a metal oxide gate dielectric using gas cluster ion beam implantation' [patent_app_type] => 1 [patent_app_number] => 9/098704 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5384 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907780.pdf [firstpage_image] =>[orig_patent_app_number] => 098704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4182370 [patent_doc_number] => 06150231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Overlay measurement technique using moire patterns' [patent_app_type] => 1 [patent_app_number] => 9/097784 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1728 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150231.pdf [firstpage_image] =>[orig_patent_app_number] => 097784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4113983 [patent_doc_number] => 06046091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Capacitor and method of making' [patent_app_type] => 1 [patent_app_number] => 9/094395 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 7863 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046091.pdf [firstpage_image] =>[orig_patent_app_number] => 094395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4097501 [patent_doc_number] => 06048746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Method for making die-compensated threshold tuning circuit' [patent_app_type] => 1 [patent_app_number] => 9/092906 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6022 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048746.pdf [firstpage_image] =>[orig_patent_app_number] => 092906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3910647 [patent_doc_number] => 06001686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method of fabricating a capacitor over a bit line of a DRAM' [patent_app_type] => 1 [patent_app_number] => 9/089245 [patent_app_country] => US [patent_app_date] => 1998-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1558 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001686.pdf [firstpage_image] =>[orig_patent_app_number] => 089245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4081111 [patent_doc_number] => 06054375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Method for making laser synthesized ceramic electronic devices and circuits' [patent_app_type] => 1 [patent_app_number] => 9/088046 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4939 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054375.pdf [firstpage_image] =>[orig_patent_app_number] => 088046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4214811 [patent_doc_number] => 06110807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Process for producing high-porosity non-evaporable getter materials' [patent_app_type] => 1 [patent_app_number] => 9/087401 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 5813 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110807.pdf [firstpage_image] =>[orig_patent_app_number] => 087401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152943 [patent_doc_number] => 06107133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method for making a five square vertical DRAM cell' [patent_app_type] => 1 [patent_app_number] => 9/085965 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 3346 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107133.pdf [firstpage_image] =>[orig_patent_app_number] => 085965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4151573 [patent_doc_number] => 06124140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method for measuring features of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/083835 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4829 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124140.pdf [firstpage_image] =>[orig_patent_app_number] => 083835 [rel_patent_id] =>[rel_patent_doc_number] =>)