
Craig Thompson
Examiner (ID: 2411)
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2811, 2812, 2813, 3999 |
| Total Applications | 616 |
| Issued Applications | 589 |
| Pending Applications | 10 |
| Abandoned Applications | 17 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4238136
[patent_doc_number] => 06080631
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Method for manufacturing self-alignment type bipolar transistor having epitaxial base layer'
[patent_app_type] => 1
[patent_app_number] => 9/083225
[patent_app_country] => US
[patent_app_date] => 1998-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 40
[patent_no_of_words] => 5330
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/080/06080631.pdf
[firstpage_image] =>[orig_patent_app_number] => 083225
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/083225 | Method for manufacturing self-alignment type bipolar transistor having epitaxial base layer | May 21, 1998 | Issued |
Array
(
[id] => 4185780
[patent_doc_number] => 06093616
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Method of manufacture of stacked gate MOS structure for multiple voltage power supply applications'
[patent_app_type] => 1
[patent_app_number] => 9/075366
[patent_app_country] => US
[patent_app_date] => 1998-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3597
[patent_no_of_claims] => 10
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/093/06093616.pdf
[firstpage_image] =>[orig_patent_app_number] => 075366
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/075366 | Method of manufacture of stacked gate MOS structure for multiple voltage power supply applications | May 10, 1998 | Issued |
Array
(
[id] => 4129869
[patent_doc_number] => 06033942
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Method of forming a metal-semiconductor field effect transistors having improved intermodulation distortion using different pinch-off voltages'
[patent_app_type] => 1
[patent_app_number] => 9/074464
[patent_app_country] => US
[patent_app_date] => 1998-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 3757
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 90
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/033/06033942.pdf
[firstpage_image] =>[orig_patent_app_number] => 074464
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/074464 | Method of forming a metal-semiconductor field effect transistors having improved intermodulation distortion using different pinch-off voltages | May 7, 1998 | Issued |
Array
(
[id] => 4180860
[patent_doc_number] => 06020213
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Method for making ferroelectric semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/069244
[patent_app_country] => US
[patent_app_date] => 1998-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1562
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/020/06020213.pdf
[firstpage_image] =>[orig_patent_app_number] => 069244
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/069244 | Method for making ferroelectric semiconductor device | Apr 28, 1998 | Issued |
Array
(
[id] => 4181705
[patent_doc_number] => 06150185
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-21
[patent_title] => 'Methods of manufacturing and testing integrated circuit field effect transistors using scanning electron microscope to detect undesired conductive material'
[patent_app_type] => 1
[patent_app_number] => 9/067195
[patent_app_country] => US
[patent_app_date] => 1998-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2790
[patent_no_of_claims] => 16
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[pdf_file] => patents/06/150/06150185.pdf
[firstpage_image] =>[orig_patent_app_number] => 067195
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/067195 | Methods of manufacturing and testing integrated circuit field effect transistors using scanning electron microscope to detect undesired conductive material | Apr 26, 1998 | Issued |
Array
(
[id] => 3944138
[patent_doc_number] => 05998259
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Method of fabricating dual cylindrical capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/066196
[patent_app_country] => US
[patent_app_date] => 1998-04-24
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 1960
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[pdf_file] => patents/05/998/05998259.pdf
[firstpage_image] =>[orig_patent_app_number] => 066196
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/066196 | Method of fabricating dual cylindrical capacitor | Apr 23, 1998 | Issued |
Array
(
[id] => 3944123
[patent_doc_number] => 05998258
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Method of forming a semiconductor device having a stacked capacitor structure'
[patent_app_type] => 1
[patent_app_number] => 9/064076
[patent_app_country] => US
[patent_app_date] => 1998-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2491
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/998/05998258.pdf
[firstpage_image] =>[orig_patent_app_number] => 064076
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/064076 | Method of forming a semiconductor device having a stacked capacitor structure | Apr 21, 1998 | Issued |
Array
(
[id] => 4108208
[patent_doc_number] => 06057249
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Method for improving optical proximity effect in storage node pattern'
[patent_app_type] => 1
[patent_app_number] => 9/063994
[patent_app_country] => US
[patent_app_date] => 1998-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 1879
[patent_no_of_claims] => 5
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[pdf_file] => patents/06/057/06057249.pdf
[firstpage_image] =>[orig_patent_app_number] => 063994
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/063994 | Method for improving optical proximity effect in storage node pattern | Apr 20, 1998 | Issued |
Array
(
[id] => 4107031
[patent_doc_number] => 06057169
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Method for I/O device layout during integrated circuit design'
[patent_app_type] => 1
[patent_app_number] => 9/062254
[patent_app_country] => US
[patent_app_date] => 1998-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 7771
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[pdf_file] => patents/06/057/06057169.pdf
[firstpage_image] =>[orig_patent_app_number] => 062254
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/062254 | Method for I/O device layout during integrated circuit design | Apr 16, 1998 | Issued |
Array
(
[id] => 4222248
[patent_doc_number] => 06010944
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'Method for increasing capacity of a capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/059364
[patent_app_country] => US
[patent_app_date] => 1998-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/010/06010944.pdf
[firstpage_image] =>[orig_patent_app_number] => 059364
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/059364 | Method for increasing capacity of a capacitor | Apr 13, 1998 | Issued |
Array
(
[id] => 4181227
[patent_doc_number] => 06020235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Channel-type stack capacitor for DRAM cell'
[patent_app_type] => 1
[patent_app_number] => 9/059290
[patent_app_country] => US
[patent_app_date] => 1998-04-14
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/020/06020235.pdf
[firstpage_image] =>[orig_patent_app_number] => 059290
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/059290 | Channel-type stack capacitor for DRAM cell | Apr 13, 1998 | Issued |
Array
(
[id] => 4213994
[patent_doc_number] => 06110751
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Tunnel junction structure and its manufacture and magnetic sensor'
[patent_app_type] => 1
[patent_app_number] => 9/057194
[patent_app_country] => US
[patent_app_date] => 1998-04-08
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[pdf_file] => patents/06/110/06110751.pdf
[firstpage_image] =>[orig_patent_app_number] => 057194
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/057194 | Tunnel junction structure and its manufacture and magnetic sensor | Apr 7, 1998 | Issued |
Array
(
[id] => 4206690
[patent_doc_number] => 06027976
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Process for making semiconductor device having nitride at silicon and polysilicon interfaces'
[patent_app_type] => 1
[patent_app_number] => 9/056963
[patent_app_country] => US
[patent_app_date] => 1998-04-08
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[pdf_file] => patents/06/027/06027976.pdf
[firstpage_image] =>[orig_patent_app_number] => 056963
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/056963 | Process for making semiconductor device having nitride at silicon and polysilicon interfaces | Apr 7, 1998 | Issued |
Array
(
[id] => 4129549
[patent_doc_number] => 06033921
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Method for depositing a material of controlled, variable thickness across a surface for planarization of that surface'
[patent_app_type] => 1
[patent_app_number] => 9/056024
[patent_app_country] => US
[patent_app_date] => 1998-04-06
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[pdf_file] => patents/06/033/06033921.pdf
[firstpage_image] =>[orig_patent_app_number] => 056024
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/056024 | Method for depositing a material of controlled, variable thickness across a surface for planarization of that surface | Apr 5, 1998 | Issued |
Array
(
[id] => 4141839
[patent_doc_number] => 06030880
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Alignment feature that avoids comet tail formation in spin-on materials and production method therefor'
[patent_app_type] => 1
[patent_app_number] => 9/055015
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[pdf_file] => patents/06/030/06030880.pdf
[firstpage_image] =>[orig_patent_app_number] => 055015
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/055015 | Alignment feature that avoids comet tail formation in spin-on materials and production method therefor | Apr 2, 1998 | Issued |
Array
(
[id] => 4222178
[patent_doc_number] => 06010939
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'Methods for making shallow trench capacitive structures'
[patent_app_type] => 1
[patent_app_number] => 9/052865
[patent_app_country] => US
[patent_app_date] => 1998-03-31
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[pdf_file] => patents/06/010/06010939.pdf
[firstpage_image] =>[orig_patent_app_number] => 052865
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/052865 | Methods for making shallow trench capacitive structures | Mar 30, 1998 | Issued |
Array
(
[id] => 4106500
[patent_doc_number] => 06022770
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'NVRAM utilizing high voltage TFT device and method for making the same'
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[patent_app_number] => 9/047155
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[pdf_file] => patents/06/022/06022770.pdf
[firstpage_image] =>[orig_patent_app_number] => 047155
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/047155 | NVRAM utilizing high voltage TFT device and method for making the same | Mar 23, 1998 | Issued |
Array
(
[id] => 3945487
[patent_doc_number] => 05953619
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Semiconductor device with perovskite capacitor and its manufacture method'
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[patent_app_number] => 9/040284
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[firstpage_image] =>[orig_patent_app_number] => 040284
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/040284 | Semiconductor device with perovskite capacitor and its manufacture method | Mar 17, 1998 | Issued |
Array
(
[id] => 3996085
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'Wafer having a laser mark on chamfered edge'
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[pdf_file] => patents/06/004/06004405.pdf
[firstpage_image] =>[orig_patent_app_number] => 036875
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/036875 | Wafer having a laser mark on chamfered edge | Mar 8, 1998 | Issued |
Array
(
[id] => 4106717
[patent_doc_number] => 06022786
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Method for manufacturing a capacitor for a semiconductor arrangement'
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/022/06022786.pdf
[firstpage_image] =>[orig_patent_app_number] => 032484
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/032484 | Method for manufacturing a capacitor for a semiconductor arrangement | Feb 26, 1998 | Issued |