Craig Thompson

Array ( [id] => 3968468 [patent_doc_number] => 05904494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Fabrication process for solid-state image pick-up device with CCD register' [patent_app_type] => 1 [patent_app_number] => 8/835412 [patent_app_country] => US [patent_app_date] => 1997-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5922 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904494.pdf [firstpage_image] =>[orig_patent_app_number] => 835412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4034391 [patent_doc_number] => 05856205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Josephson junction device of oxide superconductor having low noise level at liquid nitrogen temperature' [patent_app_type] => 1 [patent_app_number] => 8/822474 [patent_app_country] => US [patent_app_date] => 1997-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4826 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856205.pdf [firstpage_image] =>[orig_patent_app_number] => 822474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3993109 [patent_doc_number] => 05985678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method of evaluating and thermally processing semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 8/819972 [patent_app_country] => US [patent_app_date] => 1997-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5882 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985678.pdf [firstpage_image] =>[orig_patent_app_number] => 819972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057067 [patent_doc_number] => 05863834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/811300 [patent_app_country] => US [patent_app_date] => 1997-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 5035 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/863/05863834.pdf [firstpage_image] =>[orig_patent_app_number] => 811300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836785 [patent_doc_number] => 05846874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Method and apparatus for preventing cracks in semiconductor die' [patent_app_type] => 1 [patent_app_number] => 8/810494 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3385 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/846/05846874.pdf [firstpage_image] =>[orig_patent_app_number] => 810494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3994235 [patent_doc_number] => 05918126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size' [patent_app_type] => 1 [patent_app_number] => 8/805796 [patent_app_country] => US [patent_app_date] => 1997-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918126.pdf [firstpage_image] =>[orig_patent_app_number] => 805796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3965340 [patent_doc_number] => 05885904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Method to incorporate, and a device having, oxide enhancement dopants using gas immersion laser doping (GILD) for selectively growing an oxide layer' [patent_app_type] => 1 [patent_app_number] => 8/799235 [patent_app_country] => US [patent_app_date] => 1997-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5005 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/885/05885904.pdf [firstpage_image] =>[orig_patent_app_number] => 799235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4050131 [patent_doc_number] => 05943552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Schottky metal detection method' [patent_app_type] => 1 [patent_app_number] => 8/796137 [patent_app_country] => US [patent_app_date] => 1997-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 10592 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943552.pdf [firstpage_image] =>[orig_patent_app_number] => 796137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4206829 [patent_doc_number] => 06027986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Process for producing high-porosity non-evaporable getter materials' [patent_app_type] => 1 [patent_app_number] => 8/792794 [patent_app_country] => US [patent_app_date] => 1997-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4913 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/027/06027986.pdf [firstpage_image] =>[orig_patent_app_number] => 792794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3996729 [patent_doc_number] => 05911108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Method for protecting an alignment mark on a semiconductor substrate during chemical mechanical polishing and the resulting structure' [patent_app_type] => 1 [patent_app_number] => 8/791064 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 6404 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911108.pdf [firstpage_image] =>[orig_patent_app_number] => 791064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4038674 [patent_doc_number] => 05926693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Two level transistor formation for optimum silicon utilization' [patent_app_type] => 1 [patent_app_number] => 8/788376 [patent_app_country] => US [patent_app_date] => 1997-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3942 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926693.pdf [firstpage_image] =>[orig_patent_app_number] => 788376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3917950 [patent_doc_number] => 05927994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method for manufacturing thin film' [patent_app_type] => 1 [patent_app_number] => 8/782811 [patent_app_country] => US [patent_app_date] => 1997-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8894 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/927/05927994.pdf [firstpage_image] =>[orig_patent_app_number] => 782811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3759766 [patent_doc_number] => 05843831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Process independent alignment system' [patent_app_type] => 1 [patent_app_number] => 8/782702 [patent_app_country] => US [patent_app_date] => 1997-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2956 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843831.pdf [firstpage_image] =>[orig_patent_app_number] => 782702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4042375 [patent_doc_number] => 05874344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Two step source/drain anneal to prevent dopant evaporation' [patent_app_type] => 1 [patent_app_number] => 8/777544 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1385 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874344.pdf [firstpage_image] =>[orig_patent_app_number] => 777544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4181357 [patent_doc_number] => 06020244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Channel dopant implantation with automatic compensation for variations in critical dimension' [patent_app_type] => 1 [patent_app_number] => 8/777552 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2232 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020244.pdf [firstpage_image] =>[orig_patent_app_number] => 777552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3991489 [patent_doc_number] => 05891810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Process for supplying ozone (O.sub.3) to TEOS-O.sub.3 oxidizing film depositing system' [patent_app_type] => 1 [patent_app_number] => 8/773175 [patent_app_country] => US [patent_app_date] => 1996-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1998 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/891/05891810.pdf [firstpage_image] =>[orig_patent_app_number] => 773175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3768946 [patent_doc_number] => 05849628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Method of producing rough polysilicon by the use of pulsed plasma chemical vapor deposition and products produced by same' [patent_app_type] => 1 [patent_app_number] => 8/762544 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1929 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/849/05849628.pdf [firstpage_image] =>[orig_patent_app_number] => 762544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3774103 [patent_doc_number] => 05817565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method of fabricating a semiconductor memory cell having a tree-type capacitor' [patent_app_type] => 1 [patent_app_number] => 8/757672 [patent_app_country] => US [patent_app_date] => 1996-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 33 [patent_no_of_words] => 9188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/817/05817565.pdf [firstpage_image] =>[orig_patent_app_number] => 757672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4085349 [patent_doc_number] => 06017781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Method for making a thin film transistor' [patent_app_type] => 1 [patent_app_number] => 8/755734 [patent_app_country] => US [patent_app_date] => 1996-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 84 [patent_no_of_words] => 10561 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/017/06017781.pdf [firstpage_image] =>[orig_patent_app_number] => 755734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4029821 [patent_doc_number] => 05994209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Methods and apparatus for forming ultra-shallow doped regions using doped silicon oxide films' [patent_app_type] => 1 [patent_app_number] => 8/748094 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 57 [patent_no_of_words] => 42981 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994209.pdf [firstpage_image] =>[orig_patent_app_number] => 748094 [rel_patent_id] =>[rel_patent_doc_number] =>)