Search

Craig Thompson

Examiner (ID: 2411)

Most Active Art Unit
2813
Art Unit(s)
2811, 2812, 2813, 3999
Total Applications
616
Issued Applications
589
Pending Applications
10
Abandoned Applications
17

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4041978 [patent_doc_number] => 05874318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Dishing and erosion monitor structure for damascene metal processing' [patent_app_type] => 1 [patent_app_number] => 8/746532 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3263 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874318.pdf [firstpage_image] =>[orig_patent_app_number] => 746532 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746532
Dishing and erosion monitor structure for damascene metal processing Nov 12, 1996 Issued
Array ( [id] => 4004043 [patent_doc_number] => 05960272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Element-isolating construct of a semiconductor integrated circuit having an offset region between impurity doped regions, and process of manufacturing the construct' [patent_app_type] => 1 [patent_app_number] => 8/732846 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4833 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960272.pdf [firstpage_image] =>[orig_patent_app_number] => 732846 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/732846
Element-isolating construct of a semiconductor integrated circuit having an offset region between impurity doped regions, and process of manufacturing the construct Oct 14, 1996 Issued
Array ( [id] => 3771712 [patent_doc_number] => 05807776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Method of forming dynamic random access memory circuitry and dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/727922 [patent_app_country] => US [patent_app_date] => 1996-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 2311 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/807/05807776.pdf [firstpage_image] =>[orig_patent_app_number] => 727922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/727922
Method of forming dynamic random access memory circuitry and dynamic random access memory Oct 8, 1996 Issued
Array ( [id] => 4062950 [patent_doc_number] => 05866470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method of using an interface layer for stacked lamination sizing and sintering' [patent_app_type] => 1 [patent_app_number] => 8/727109 [patent_app_country] => US [patent_app_date] => 1996-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3355 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/866/05866470.pdf [firstpage_image] =>[orig_patent_app_number] => 727109 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/727109
Method of using an interface layer for stacked lamination sizing and sintering Oct 7, 1996 Issued
Array ( [id] => 3950634 [patent_doc_number] => 05899733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method for the implantation of dopant' [patent_app_type] => 1 [patent_app_number] => 8/725236 [patent_app_country] => US [patent_app_date] => 1996-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1691 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/899/05899733.pdf [firstpage_image] =>[orig_patent_app_number] => 725236 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/725236
Method for the implantation of dopant Oct 2, 1996 Issued
Array ( [id] => 4000728 [patent_doc_number] => 05858843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Low temperature method of forming gate electrode and gate dielectric' [patent_app_type] => 1 [patent_app_number] => 8/722606 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 3842 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/858/05858843.pdf [firstpage_image] =>[orig_patent_app_number] => 722606 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/722606
Low temperature method of forming gate electrode and gate dielectric Sep 26, 1996 Issued
Array ( [id] => 4069949 [patent_doc_number] => 05933742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Multi-crown capacitor for high density DRAMS' [patent_app_type] => 1 [patent_app_number] => 8/708236 [patent_app_country] => US [patent_app_date] => 1996-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2805 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933742.pdf [firstpage_image] =>[orig_patent_app_number] => 708236 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708236
Multi-crown capacitor for high density DRAMS Sep 5, 1996 Issued
Array ( [id] => 3938021 [patent_doc_number] => 05872028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Method of forming power semiconductor devices with controllable integrated buffer' [patent_app_type] => 1 [patent_app_number] => 8/708712 [patent_app_country] => US [patent_app_date] => 1996-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2418 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872028.pdf [firstpage_image] =>[orig_patent_app_number] => 708712 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708712
Method of forming power semiconductor devices with controllable integrated buffer Sep 4, 1996 Issued
Array ( [id] => 3867236 [patent_doc_number] => 05837563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Self aligned barrier process for small pixel virtual phase charged coupled devices' [patent_app_type] => 1 [patent_app_number] => 8/703262 [patent_app_country] => US [patent_app_date] => 1996-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1073 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/837/05837563.pdf [firstpage_image] =>[orig_patent_app_number] => 703262 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/703262
Self aligned barrier process for small pixel virtual phase charged coupled devices Aug 25, 1996 Issued
Array ( [id] => 3808221 [patent_doc_number] => 05811350 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method of forming contact openings and an electronic component formed from the same and other methods' [patent_app_type] => 1 [patent_app_number] => 8/670318 [patent_app_country] => US [patent_app_date] => 1996-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3275 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811350.pdf [firstpage_image] =>[orig_patent_app_number] => 670318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/670318
Method of forming contact openings and an electronic component formed from the same and other methods Aug 21, 1996 Issued
Array ( [id] => 3926558 [patent_doc_number] => 05877095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Method of fabricating a semiconductor device having a silicon nitride film made of silane, ammonia and nitrogen' [patent_app_type] => 1 [patent_app_number] => 8/698841 [patent_app_country] => US [patent_app_date] => 1996-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 11022 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877095.pdf [firstpage_image] =>[orig_patent_app_number] => 698841 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/698841
Method of fabricating a semiconductor device having a silicon nitride film made of silane, ammonia and nitrogen Aug 15, 1996 Issued
Array ( [id] => 3768401 [patent_doc_number] => 05773358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Method of forming a field effect transistor and method of forming CMOS integrated circuitry' [patent_app_type] => 1 [patent_app_number] => 8/695407 [patent_app_country] => US [patent_app_date] => 1996-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2938 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773358.pdf [firstpage_image] =>[orig_patent_app_number] => 695407 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/695407
Method of forming a field effect transistor and method of forming CMOS integrated circuitry Aug 11, 1996 Issued
Array ( [id] => 3980331 [patent_doc_number] => 05910013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Process for manufacturing a solid-state pick-up device' [patent_app_type] => 1 [patent_app_number] => 8/691250 [patent_app_country] => US [patent_app_date] => 1996-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3811 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910013.pdf [firstpage_image] =>[orig_patent_app_number] => 691250 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/691250
Process for manufacturing a solid-state pick-up device Aug 1, 1996 Issued
Array ( [id] => 4023743 [patent_doc_number] => 05882962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method of fabricating MOS transistor having a P.sup.+ -polysilicon gate' [patent_app_type] => 1 [patent_app_number] => 8/688168 [patent_app_country] => US [patent_app_date] => 1996-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3246 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/882/05882962.pdf [firstpage_image] =>[orig_patent_app_number] => 688168 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/688168
Method of fabricating MOS transistor having a P.sup.+ -polysilicon gate Jul 28, 1996 Issued
Array ( [id] => 4034508 [patent_doc_number] => 05856213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Method of fabricating a programmable function system block using two masks and a sacrificial oxide layer between the bottom metal and an amorphous silicon antifuse structure' [patent_app_type] => 1 [patent_app_number] => 8/687234 [patent_app_country] => US [patent_app_date] => 1996-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2250 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856213.pdf [firstpage_image] =>[orig_patent_app_number] => 687234 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/687234
Method of fabricating a programmable function system block using two masks and a sacrificial oxide layer between the bottom metal and an amorphous silicon antifuse structure Jul 24, 1996 Issued
Array ( [id] => 4062521 [patent_doc_number] => 05866439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method of fabricating an end face light emitting type light-emitting diode and a light-emitting diode array device' [patent_app_type] => 1 [patent_app_number] => 8/687046 [patent_app_country] => US [patent_app_date] => 1996-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 6153 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/866/05866439.pdf [firstpage_image] =>[orig_patent_app_number] => 687046 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/687046
Method of fabricating an end face light emitting type light-emitting diode and a light-emitting diode array device Jul 17, 1996 Issued
Array ( [id] => 3877384 [patent_doc_number] => 05804489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method of manufacturing a crown shape capacitor in semiconductor memory using a single step etching' [patent_app_type] => 1 [patent_app_number] => 8/679196 [patent_app_country] => US [patent_app_date] => 1996-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1859 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804489.pdf [firstpage_image] =>[orig_patent_app_number] => 679196 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/679196
Method of manufacturing a crown shape capacitor in semiconductor memory using a single step etching Jul 11, 1996 Issued
Array ( [id] => 3759582 [patent_doc_number] => 05851848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Method and apparatus for aligning the position of die on a wafer table' [patent_app_type] => 1 [patent_app_number] => 8/667246 [patent_app_country] => US [patent_app_date] => 1996-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3014 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/851/05851848.pdf [firstpage_image] =>[orig_patent_app_number] => 667246 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/667246
Method and apparatus for aligning the position of die on a wafer table Jun 19, 1996 Issued
08/663708 METHOD OF CONSTRUCTING A FUSE FOR A SEMICONDUCTOR DEVICE AND CIRCUIT USING SAME Jun 13, 1996 Abandoned
Array ( [id] => 3886101 [patent_doc_number] => 05893745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Methods of forming semiconductor-on-insulator substrates' [patent_app_type] => 1 [patent_app_number] => 8/664958 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2005 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893745.pdf [firstpage_image] =>[orig_patent_app_number] => 664958 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664958
Methods of forming semiconductor-on-insulator substrates Jun 12, 1996 Issued
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