Search

Craig Thompson

Examiner (ID: 14661)

Most Active Art Unit
2813
Art Unit(s)
2811, 2813, 2812, 3999
Total Applications
616
Issued Applications
589
Pending Applications
10
Abandoned Applications
17

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1212693 [patent_doc_number] => 06709914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Manufacturing process of pn junction diode device and pn junction diode device' [patent_app_type] => B2 [patent_app_number] => 10/331646 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5037 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/709/06709914.pdf [firstpage_image] =>[orig_patent_app_number] => 10331646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331646
Manufacturing process of pn junction diode device and pn junction diode device Dec 30, 2002 Issued
Array ( [id] => 7625595 [patent_doc_number] => 06723574 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Method for quantifying uniformity patterns and including expert knowledge for tool development and control' [patent_app_type] => B1 [patent_app_number] => 10/328876 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6034 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/723/06723574.pdf [firstpage_image] =>[orig_patent_app_number] => 10328876 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/328876
Method for quantifying uniformity patterns and including expert knowledge for tool development and control Dec 22, 2002 Issued
Array ( [id] => 7408576 [patent_doc_number] => 20040106228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Substrate based ESD network protection method for flip chip design' [patent_app_type] => new [patent_app_number] => 10/308446 [patent_app_country] => US [patent_app_date] => 2002-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3468 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20040106228.pdf [firstpage_image] =>[orig_patent_app_number] => 10308446 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/308446
Substrate based ESD network protection method for flip chip design Dec 2, 2002 Issued
Array ( [id] => 1188854 [patent_doc_number] => 06734085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Anti-type dosage as LDD implant' [patent_app_type] => B1 [patent_app_number] => 10/307676 [patent_app_country] => US [patent_app_date] => 2002-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3436 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734085.pdf [firstpage_image] =>[orig_patent_app_number] => 10307676 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/307676
Anti-type dosage as LDD implant Dec 1, 2002 Issued
Array ( [id] => 7451599 [patent_doc_number] => 20040099917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Wafer-level packaging of electronic devices before singulation' [patent_app_type] => new [patent_app_number] => 10/306356 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2039 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20040099917.pdf [firstpage_image] =>[orig_patent_app_number] => 10306356 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/306356
Wafer-level packaging of electronic devices before singulation Nov 26, 2002 Issued
Array ( [id] => 6655974 [patent_doc_number] => 20030132496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Compound semiconductor device, method for producing thereof and high frequency module using thereof' [patent_app_type] => new [patent_app_number] => 10/298655 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4100 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20030132496.pdf [firstpage_image] =>[orig_patent_app_number] => 10298655 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/298655
Compound semiconductor device, method for producing thereof and high frequency module using thereof Nov 18, 2002 Abandoned
Array ( [id] => 6816119 [patent_doc_number] => 20030067077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Organic copper diffusion barrier layer' [patent_app_type] => new [patent_app_number] => 10/298616 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2519 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20030067077.pdf [firstpage_image] =>[orig_patent_app_number] => 10298616 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/298616
Organic copper diffusion barrier layer Nov 18, 2002 Abandoned
Array ( [id] => 1212754 [patent_doc_number] => 06709946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Method for interconnecting anodes and cathodes in a flat capacitor' [patent_app_type] => B2 [patent_app_number] => 10/299234 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5462 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/709/06709946.pdf [firstpage_image] =>[orig_patent_app_number] => 10299234 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/299234
Method for interconnecting anodes and cathodes in a flat capacitor Nov 18, 2002 Issued
Array ( [id] => 6699431 [patent_doc_number] => 20030222311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Amorphous silicon thin film transistor-liquid crystal display device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/293095 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7381 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20030222311.pdf [firstpage_image] =>[orig_patent_app_number] => 10293095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/293095
Amorphous silicon thin-film transistor liquid crystal display Nov 12, 2002 Issued
Array ( [id] => 6861205 [patent_doc_number] => 20030092213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Semiconductor device and method for its fabrication' [patent_app_type] => new [patent_app_number] => 10/292875 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 17945 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20030092213.pdf [firstpage_image] =>[orig_patent_app_number] => 10292875 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292875
Method for fabricating a semiconductor device Nov 12, 2002 Issued
Array ( [id] => 6701690 [patent_doc_number] => 20030224570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Storage capacitor of planar display and process for fabricating same' [patent_app_type] => new [patent_app_number] => 10/292292 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20030224570.pdf [firstpage_image] =>[orig_patent_app_number] => 10292292 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292292
Storage capacitor of planar display and process for fabricating same Nov 11, 2002 Issued
Array ( [id] => 6861216 [patent_doc_number] => 20030092224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Semiconductor doping method and liquid crystal display device fabricating method using the same' [patent_app_type] => new [patent_app_number] => 10/291376 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4834 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20030092224.pdf [firstpage_image] =>[orig_patent_app_number] => 10291376 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291376
Semiconductor doping method and liquid crystal display device fabricating method using the same Nov 11, 2002 Issued
Array ( [id] => 1216554 [patent_doc_number] => 06706640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Metal silicide etch resistant plasma etch method' [patent_app_type] => B1 [patent_app_number] => 10/292355 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/706/06706640.pdf [firstpage_image] =>[orig_patent_app_number] => 10292355 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292355
Metal silicide etch resistant plasma etch method Nov 11, 2002 Issued
Array ( [id] => 1235612 [patent_doc_number] => 06689639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Method of making semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/291766 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 40 [patent_no_of_words] => 11298 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/689/06689639.pdf [firstpage_image] =>[orig_patent_app_number] => 10291766 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291766
Method of making semiconductor device Nov 11, 2002 Issued
Array ( [id] => 1226017 [patent_doc_number] => 06704913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-09 [patent_title] => 'In situ wafer heat for reduced backside contamination' [patent_app_type] => B2 [patent_app_number] => 10/291166 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7390 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704913.pdf [firstpage_image] =>[orig_patent_app_number] => 10291166 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291166
In situ wafer heat for reduced backside contamination Nov 7, 2002 Issued
Array ( [id] => 7365134 [patent_doc_number] => 20040092062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Planarizing gate material to improve gate critical dimension in semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/290276 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092062.pdf [firstpage_image] =>[orig_patent_app_number] => 10290276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290276
Method using planarizing gate material to improve gate critical dimension in semiconductor devices Nov 7, 2002 Issued
Array ( [id] => 6792176 [patent_doc_number] => 20030087520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Process for removing an underlying layer and depositing a barrier layer in one reactor' [patent_app_type] => new [patent_app_number] => 10/290746 [patent_app_country] => US [patent_app_date] => 2002-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5674 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20030087520.pdf [firstpage_image] =>[orig_patent_app_number] => 10290746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290746
Process for removing an underlying layer and depositing a barrier layer in one reactor Nov 6, 2002 Issued
Array ( [id] => 1196571 [patent_doc_number] => 06727117 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Semiconductor substrate having copper/diamond composite material and method of making same' [patent_app_type] => B1 [patent_app_number] => 10/291126 [patent_app_country] => US [patent_app_date] => 2002-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2753 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727117.pdf [firstpage_image] =>[orig_patent_app_number] => 10291126 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291126
Semiconductor substrate having copper/diamond composite material and method of making same Nov 6, 2002 Issued
Array ( [id] => 1128283 [patent_doc_number] => 06791149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Diffusion barrier layer for semiconductor wafer fabrication' [patent_app_type] => B2 [patent_app_number] => 10/287569 [patent_app_country] => US [patent_app_date] => 2002-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3859 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791149.pdf [firstpage_image] =>[orig_patent_app_number] => 10287569 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/287569
Diffusion barrier layer for semiconductor wafer fabrication Nov 3, 2002 Issued
Array ( [id] => 1097428 [patent_doc_number] => 06822299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Boron-doped titanium nitride layer for high aspect ratio semiconductor devices' [patent_app_type] => B2 [patent_app_number] => 10/287203 [patent_app_country] => US [patent_app_date] => 2002-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5123 [patent_no_of_claims] => 95 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/822/06822299.pdf [firstpage_image] =>[orig_patent_app_number] => 10287203 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/287203
Boron-doped titanium nitride layer for high aspect ratio semiconductor devices Nov 3, 2002 Issued
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