
Cuong B. Nguyen
Examiner (ID: 761, Phone: (571)270-1509 , Office: P/2818 )
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2818 |
| Total Applications | 1117 |
| Issued Applications | 910 |
| Pending Applications | 105 |
| Abandoned Applications | 124 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19546470
[patent_doc_number] => 20240363506
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/594792
[patent_app_country] => US
[patent_app_date] => 2024-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14492
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594792
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/594792 | Semiconductor device and manufacturing method thereof | Mar 3, 2024 | Issued |
Array
(
[id] => 20198497
[patent_doc_number] => 20250275207
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-28
[patent_title] => HYBRID GaN AND BCD DEVICES USING HETEROEPITAXY ON SILICON
[patent_app_type] => utility
[patent_app_number] => 18/589545
[patent_app_country] => US
[patent_app_date] => 2024-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589545
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/589545 | HYBRID GaN AND BCD DEVICES USING HETEROEPITAXY ON SILICON | Feb 27, 2024 | Pending |
Array
(
[id] => 20198425
[patent_doc_number] => 20250275135
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-28
[patent_title] => MULTI-TIER MEMORY ARRAY INCLUDING LATERALLY-STAGGERED STAIRCASES AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/590048
[patent_app_country] => US
[patent_app_date] => 2024-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13320
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590048
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/590048 | MULTI-TIER MEMORY ARRAY INCLUDING LATERALLY-STAGGERED STAIRCASES AND METHOD OF MAKING THE SAME | Feb 27, 2024 | Pending |
Array
(
[id] => 19931609
[patent_doc_number] => 12304806
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-20
[patent_title] => Actuator device
[patent_app_type] => utility
[patent_app_number] => 18/581466
[patent_app_country] => US
[patent_app_date] => 2024-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3573
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581466
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/581466 | Actuator device | Feb 19, 2024 | Issued |
Array
(
[id] => 19386858
[patent_doc_number] => 20240276728
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/438263
[patent_app_country] => US
[patent_app_date] => 2024-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12016
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438263
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/438263 | SEMICONDUCTOR DEVICE | Feb 8, 2024 | Pending |
Array
(
[id] => 20155076
[patent_doc_number] => 20250254914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-08-07
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/431140
[patent_app_country] => US
[patent_app_date] => 2024-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3368
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431140
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/431140 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Feb 1, 2024 | Pending |
Array
(
[id] => 20002385
[patent_doc_number] => 20250140607
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-01
[patent_title] => THERMAL CONDUCTIVE BARRIER LAYER IN INTERCONNECT STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/425264
[patent_app_country] => US
[patent_app_date] => 2024-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3619
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425264
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/425264 | THERMAL CONDUCTIVE BARRIER LAYER IN INTERCONNECT STRUCTURE | Jan 28, 2024 | Pending |
Array
(
[id] => 20141082
[patent_doc_number] => 20250248126
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-31
[patent_title] => THREE DIMENSIONAL SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/423827
[patent_app_country] => US
[patent_app_date] => 2024-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423827
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/423827 | THREE DIMENSIONAL SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | Jan 25, 2024 | Pending |
Array
(
[id] => 19360648
[patent_doc_number] => 20240262682
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => METHOD FOR PRODUCING A MICROMECHANICAL DEVICE COMPRISING A CAVITY HAVING A MELT SEAL
[patent_app_type] => utility
[patent_app_number] => 18/423008
[patent_app_country] => US
[patent_app_date] => 2024-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3412
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423008
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/423008 | METHOD FOR PRODUCING A MICROMECHANICAL DEVICE COMPRISING A CAVITY HAVING A MELT SEAL | Jan 24, 2024 | Pending |
Array
(
[id] => 19621565
[patent_doc_number] => 20240407245
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => DEPOSITION MASK, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE MANUFACTURED USING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/418645
[patent_app_country] => US
[patent_app_date] => 2024-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11545
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418645
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/418645 | DEPOSITION MASK, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE MANUFACTURED USING THE SAME | Jan 21, 2024 | Pending |
Array
(
[id] => 20111575
[patent_doc_number] => 12362311
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Anisotropic conductive film with carbon-based conductive regions having void space and related semiconductor device assemblies and methods
[patent_app_type] => utility
[patent_app_number] => 18/419382
[patent_app_country] => US
[patent_app_date] => 2024-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 37
[patent_no_of_words] => 6245
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419382
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/419382 | Anisotropic conductive film with carbon-based conductive regions having void space and related semiconductor device assemblies and methods | Jan 21, 2024 | Issued |
Array
(
[id] => 19597087
[patent_doc_number] => 12154941
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-11-26
[patent_title] => Power MOSFET with gate-source ESD diode structure
[patent_app_type] => utility
[patent_app_number] => 18/416776
[patent_app_country] => US
[patent_app_date] => 2024-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 31
[patent_no_of_words] => 9085
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416776
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/416776 | Power MOSFET with gate-source ESD diode structure | Jan 17, 2024 | Issued |
Array
(
[id] => 20021768
[patent_doc_number] => 20250159990
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-15
[patent_title] => DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/412658
[patent_app_country] => US
[patent_app_date] => 2024-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1204
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412658
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/412658 | DISPLAY PANEL AND DISPLAY DEVICE | Jan 14, 2024 | Pending |
Array
(
[id] => 20104723
[patent_doc_number] => 20250234659
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-17
[patent_title] => SEMICONDUCTOR STRUCTURE INCLUDING PHOTODETECTOR AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/409806
[patent_app_country] => US
[patent_app_date] => 2024-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2200
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409806
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/409806 | SEMICONDUCTOR STRUCTURE INCLUDING PHOTODETECTOR AND MANUFACTURING METHOD THEREOF | Jan 10, 2024 | Pending |
Array
(
[id] => 20104667
[patent_doc_number] => 20250234603
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-17
[patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/409827
[patent_app_country] => US
[patent_app_date] => 2024-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5430
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409827
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/409827 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | Jan 10, 2024 | Pending |
Array
(
[id] => 19604901
[patent_doc_number] => 20240395781
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/407893
[patent_app_country] => US
[patent_app_date] => 2024-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13998
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407893
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/407893 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME | Jan 8, 2024 | Pending |
Array
(
[id] => 19392861
[patent_doc_number] => 20240282731
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => HYBRID BONDING FOR SEMICONDUCTOR DEVICE ASSEMBLIES
[patent_app_type] => utility
[patent_app_number] => 18/406068
[patent_app_country] => US
[patent_app_date] => 2024-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7089
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406068
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/406068 | HYBRID BONDING FOR SEMICONDUCTOR DEVICE ASSEMBLIES | Jan 4, 2024 | Pending |
Array
(
[id] => 19321523
[patent_doc_number] => 20240243070
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/402821
[patent_app_country] => US
[patent_app_date] => 2024-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5020
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402821
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/402821 | ELECTRONIC DEVICE | Jan 2, 2024 | Pending |
Array
(
[id] => 19577457
[patent_doc_number] => 20240381749
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-14
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/402310
[patent_app_country] => US
[patent_app_date] => 2024-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6298
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402310
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/402310 | DISPLAY DEVICE | Jan 1, 2024 | Pending |
Array
(
[id] => 19305956
[patent_doc_number] => 20240234536
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2024-07-11
[patent_title] => SILICON CARBIDE MOSFET DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/398686
[patent_app_country] => US
[patent_app_date] => 2023-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5668
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 295
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18398686
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/398686 | Silicon carbide MOSFET device and manufacturing method thereof | Dec 27, 2023 | Issued |