
Cynthia Francisca Collado
Examiner (ID: 146, Phone: (571)272-8315 , Office: P/3781 )
| Most Active Art Unit | 3781 |
| Art Unit(s) | 3618, 3733, 3781 |
| Total Applications | 1071 |
| Issued Applications | 585 |
| Pending Applications | 8 |
| Abandoned Applications | 477 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 788350
[patent_doc_number] => 06987283
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-17
[patent_title] => 'Semiconductor device structure'
[patent_app_type] => utility
[patent_app_number] => 10/180015
[patent_app_country] => US
[patent_app_date] => 2002-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 30
[patent_no_of_words] => 11378
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/987/06987283.pdf
[firstpage_image] =>[orig_patent_app_number] => 10180015
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/180015 | Semiconductor device structure | Jun 26, 2002 | Issued |
Array
(
[id] => 1374667
[patent_doc_number] => 06566722
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-20
[patent_title] => 'Photo sensor in a photo diode on a semiconductor wafer'
[patent_app_type] => B1
[patent_app_number] => 10/064256
[patent_app_country] => US
[patent_app_date] => 2002-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2418
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/566/06566722.pdf
[firstpage_image] =>[orig_patent_app_number] => 10064256
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/064256 | Photo sensor in a photo diode on a semiconductor wafer | Jun 25, 2002 | Issued |
Array
(
[id] => 1223721
[patent_doc_number] => 06699760
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-02
[patent_title] => 'Method for growing layers of group III-nitride semiconductor having electrically passivated threading defects'
[patent_app_type] => B2
[patent_app_number] => 10/179806
[patent_app_country] => US
[patent_app_date] => 2002-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 5941
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/699/06699760.pdf
[firstpage_image] =>[orig_patent_app_number] => 10179806
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/179806 | Method for growing layers of group III-nitride semiconductor having electrically passivated threading defects | Jun 24, 2002 | Issued |
Array
(
[id] => 7631017
[patent_doc_number] => 06635915
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-10-21
[patent_title] => 'Semiconductor device having trench capacitor formed in SOI substrate'
[patent_app_type] => B2
[patent_app_number] => 10/178749
[patent_app_country] => US
[patent_app_date] => 2002-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2722
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/635/06635915.pdf
[firstpage_image] =>[orig_patent_app_number] => 10178749
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/178749 | Semiconductor device having trench capacitor formed in SOI substrate | Jun 24, 2002 | Issued |
Array
(
[id] => 6823796
[patent_doc_number] => 20030234418
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-25
[patent_title] => 'MEMORY STRUCTURE HAVING REQUIRED SCALE SPACERS'
[patent_app_type] => new
[patent_app_number] => 10/177599
[patent_app_country] => US
[patent_app_date] => 2002-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2899
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0234/20030234418.pdf
[firstpage_image] =>[orig_patent_app_number] => 10177599
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/177599 | Memory structure and method for manufacturing the same | Jun 18, 2002 | Issued |
Array
(
[id] => 1280793
[patent_doc_number] => 06642074
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-04
[patent_title] => 'Method for manufacturing thin film transistor array panel for LCD having a quadruple layer by a second photolithography process'
[patent_app_type] => B2
[patent_app_number] => 10/172982
[patent_app_country] => US
[patent_app_date] => 2002-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 58
[patent_figures_cnt] => 66
[patent_no_of_words] => 15712
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/642/06642074.pdf
[firstpage_image] =>[orig_patent_app_number] => 10172982
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/172982 | Method for manufacturing thin film transistor array panel for LCD having a quadruple layer by a second photolithography process | Jun 17, 2002 | Issued |
Array
(
[id] => 6107155
[patent_doc_number] => 20020171108
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'Thin film transistor array substrate for liquid cystal display and a method for fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/171767
[patent_app_country] => US
[patent_app_date] => 2002-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4457
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0171/20020171108.pdf
[firstpage_image] =>[orig_patent_app_number] => 10171767
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/171767 | Thin film transistor array substrate for liquid crystal display structure | Jun 16, 2002 | Issued |
Array
(
[id] => 6805088
[patent_doc_number] => 20030232482
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-18
[patent_title] => 'MICROELECTRONIC FABRICATION HAVING FABRICATED THEREIN SPATIALLY OVERLAPPING CAPACITOR STRUCTURES'
[patent_app_type] => new
[patent_app_number] => 10/172137
[patent_app_country] => US
[patent_app_date] => 2002-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4147
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0232/20030232482.pdf
[firstpage_image] =>[orig_patent_app_number] => 10172137
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/172137 | MICROELECTRONIC FABRICATION HAVING FABRICATED THEREIN SPATIALLY OVERLAPPING CAPACITOR STRUCTURES | Jun 13, 2002 | Abandoned |
Array
(
[id] => 6444906
[patent_doc_number] => 20020149093
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-17
[patent_title] => 'Method for manufacturing a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/172701
[patent_app_country] => US
[patent_app_date] => 2002-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3246
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0149/20020149093.pdf
[firstpage_image] =>[orig_patent_app_number] => 10172701
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/172701 | Method for manufacturing a semiconductor device | Jun 13, 2002 | Issued |
Array
(
[id] => 1095822
[patent_doc_number] => 06821799
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-23
[patent_title] => 'Method of fabricating a multi-color light emissive display'
[patent_app_type] => B2
[patent_app_number] => 10/171147
[patent_app_country] => US
[patent_app_date] => 2002-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 12
[patent_no_of_words] => 6102
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/821/06821799.pdf
[firstpage_image] =>[orig_patent_app_number] => 10171147
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/171147 | Method of fabricating a multi-color light emissive display | Jun 12, 2002 | Issued |
Array
(
[id] => 6469543
[patent_doc_number] => 20020151151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-17
[patent_title] => 'Honeycomb capacitor and method of fabrication'
[patent_app_type] => new
[patent_app_number] => 10/170998
[patent_app_country] => US
[patent_app_date] => 2002-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 3672
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20020151151.pdf
[firstpage_image] =>[orig_patent_app_number] => 10170998
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/170998 | Method of fabricating a high surface area capacitor electrode | Jun 12, 2002 | Issued |
Array
(
[id] => 7620137
[patent_doc_number] => 06943044
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-09-13
[patent_title] => 'Method of high speed data rate testing'
[patent_app_type] => utility
[patent_app_number] => 10/167858
[patent_app_country] => US
[patent_app_date] => 2002-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3230
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/943/06943044.pdf
[firstpage_image] =>[orig_patent_app_number] => 10167858
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/167858 | Method of high speed data rate testing | Jun 10, 2002 | Issued |
Array
(
[id] => 1228231
[patent_doc_number] => 06696337
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-24
[patent_title] => 'Method of manufacturing a semiconductor integrated circuit device having a memory cell array and a peripheral circuit region'
[patent_app_type] => B2
[patent_app_number] => 10/166013
[patent_app_country] => US
[patent_app_date] => 2002-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 71
[patent_no_of_words] => 19190
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/696/06696337.pdf
[firstpage_image] =>[orig_patent_app_number] => 10166013
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/166013 | Method of manufacturing a semiconductor integrated circuit device having a memory cell array and a peripheral circuit region | Jun 10, 2002 | Issued |
Array
(
[id] => 1424625
[patent_doc_number] => 06515369
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-04
[patent_title] => 'High performance system-on-chip using post passivation process'
[patent_app_type] => B1
[patent_app_number] => 10/156412
[patent_app_country] => US
[patent_app_date] => 2002-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 8666
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 337
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/515/06515369.pdf
[firstpage_image] =>[orig_patent_app_number] => 10156412
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/156412 | High performance system-on-chip using post passivation process | May 27, 2002 | Issued |
Array
(
[id] => 1536467
[patent_doc_number] => 06489656
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Resistor for high performance system-on-chip using post passivation process'
[patent_app_type] => B1
[patent_app_number] => 10/156589
[patent_app_country] => US
[patent_app_date] => 2002-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 8685
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/489/06489656.pdf
[firstpage_image] =>[orig_patent_app_number] => 10156589
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/156589 | Resistor for high performance system-on-chip using post passivation process | May 27, 2002 | Issued |
Array
(
[id] => 1536441
[patent_doc_number] => 06489647
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Capacitor for high performance system-on-chip using post passivation process structure'
[patent_app_type] => B1
[patent_app_number] => 10/156590
[patent_app_country] => US
[patent_app_date] => 2002-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 8684
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 492
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/489/06489647.pdf
[firstpage_image] =>[orig_patent_app_number] => 10156590
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/156590 | Capacitor for high performance system-on-chip using post passivation process structure | May 27, 2002 | Issued |
Array
(
[id] => 6801318
[patent_doc_number] => 20030096483
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-22
[patent_title] => 'METHOD OF MANUFACTURING MOS TRANSISTOR WITH FLUORIDE IMPLANTATION ON SILICON NITRIDE ETCHING STOP LAYER'
[patent_app_type] => new
[patent_app_number] => 10/154604
[patent_app_country] => US
[patent_app_date] => 2002-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1762
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0096/20030096483.pdf
[firstpage_image] =>[orig_patent_app_number] => 10154604
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/154604 | Method of manufacturing MOS transistor with fluoride implantation on silicon nitride etching stop layer | May 21, 2002 | Issued |
Array
(
[id] => 968495
[patent_doc_number] => 06939769
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-06
[patent_title] => 'Method for manufacturing a semiconductor device with using double implanting boron and boron difluoride'
[patent_app_type] => utility
[patent_app_number] => 10/138556
[patent_app_country] => US
[patent_app_date] => 2002-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 3065
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/939/06939769.pdf
[firstpage_image] =>[orig_patent_app_number] => 10138556
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/138556 | Method for manufacturing a semiconductor device with using double implanting boron and boron difluoride | May 5, 2002 | Issued |
Array
(
[id] => 1249105
[patent_doc_number] => 06674128
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-06
[patent_title] => 'Semiconductor-on-insulator device with thermoelectric cooler on surface'
[patent_app_type] => B1
[patent_app_number] => 10/135008
[patent_app_country] => US
[patent_app_date] => 2002-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 15
[patent_no_of_words] => 3812
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/674/06674128.pdf
[firstpage_image] =>[orig_patent_app_number] => 10135008
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/135008 | Semiconductor-on-insulator device with thermoelectric cooler on surface | Apr 28, 2002 | Issued |
Array
(
[id] => 1330594
[patent_doc_number] => 06600203
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-29
[patent_title] => 'Semiconductor device with silicon carbide suppression layer for preventing extension of micropipe'
[patent_app_type] => B2
[patent_app_number] => 10/127126
[patent_app_country] => US
[patent_app_date] => 2002-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 9066
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/600/06600203.pdf
[firstpage_image] =>[orig_patent_app_number] => 10127126
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/127126 | Semiconductor device with silicon carbide suppression layer for preventing extension of micropipe | Apr 21, 2002 | Issued |