Search

Cynthia H. Britt

Examiner (ID: 10505, Phone: (571)272-3815 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2117, 2133, 2138, 2111
Total Applications
1872
Issued Applications
1708
Pending Applications
85
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20153168 [patent_doc_number] => 20250253006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => MEMORY REPAIR FLAG TOKEN COUNTER [patent_app_type] => utility [patent_app_number] => 19/046319 [patent_app_country] => US [patent_app_date] => 2025-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19046319 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/046319
MEMORY REPAIR FLAG TOKEN COUNTER Feb 4, 2025 Pending
Array ( [id] => 20234369 [patent_doc_number] => 20250291688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => ERROR RATE MEASUREMENT APPARATUS AND SIGNAL DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 19/024234 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19024234 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/024234
ERROR RATE MEASUREMENT APPARATUS AND SIGNAL DETECTION METHOD Jan 15, 2025 Pending
Array ( [id] => 20101778 [patent_doc_number] => 20250231714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => MEMORY COMPONENT HAVING INTERNAL READ-MODIFY-WRITE OPERATION [patent_app_type] => utility [patent_app_number] => 19/019182 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19019182 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/019182
MEMORY COMPONENT HAVING INTERNAL READ-MODIFY-WRITE OPERATION Jan 12, 2025 Pending
Array ( [id] => 20009620 [patent_doc_number] => 20250147842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => MEMORY SYSTEM AND NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 19/013074 [patent_app_country] => US [patent_app_date] => 2025-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19013074 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/013074
MEMORY SYSTEM AND NONVOLATILE MEMORY Jan 7, 2025 Pending
Array ( [id] => 19986775 [patent_doc_number] => 20250124997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => METHOD FOR ERROR CORRECTION CODING WITH MULTIPLE HASH GROUPINGS AND DEVICE FOR PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/991656 [patent_app_country] => US [patent_app_date] => 2024-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18991656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/991656
METHOD FOR ERROR CORRECTION CODING WITH MULTIPLE HASH GROUPINGS AND DEVICE FOR PERFORMING THE SAME Dec 21, 2024 Pending
Array ( [id] => 20103665 [patent_doc_number] => 20250233601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => ENCODING METADATA INFORMATION IN A CODEWORD [patent_app_type] => utility [patent_app_number] => 18/987205 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18987205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/987205
ENCODING METADATA INFORMATION IN A CODEWORD Dec 18, 2024 Pending
Array ( [id] => 19987601 [patent_doc_number] => 20250125823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => CONCATENATED POLAR CODE WITH ADAPTIVE ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 18/986548 [patent_app_country] => US [patent_app_date] => 2024-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18986548 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/986548
CONCATENATED POLAR CODE WITH ADAPTIVE ERROR DETECTION Dec 17, 2024 Pending
Array ( [id] => 20409791 [patent_doc_number] => 20250378900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => DETERMINING HEALTH OF A NON-VOLATILE MEMORY DEVICE BASED ON A PREDETERMINED DATA PATTERN [patent_app_type] => utility [patent_app_number] => 18/984990 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18984990 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/984990
DETERMINING HEALTH OF A NON-VOLATILE MEMORY DEVICE BASED ON A PREDETERMINED DATA PATTERN Dec 16, 2024 Pending
Array ( [id] => 19880478 [patent_doc_number] => 20250112735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => SHORT LATENCY FAST RETRANSMISSION TRIGGERING [patent_app_type] => utility [patent_app_number] => 18/979060 [patent_app_country] => US [patent_app_date] => 2024-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18979060 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/979060
SHORT LATENCY FAST RETRANSMISSION TRIGGERING Dec 11, 2024 Pending
Array ( [id] => 20428290 [patent_doc_number] => 20250390382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => ERROR CORRECTION CIRCUIT, STORAGE CONTROLLER INCLUDING ERROR CORRECTION CIRCUIT, AND STORAGE DEVICE INCLUDING STORAGE CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/977727 [patent_app_country] => US [patent_app_date] => 2024-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/977727
ERROR CORRECTION CIRCUIT, STORAGE CONTROLLER INCLUDING ERROR CORRECTION CIRCUIT, AND STORAGE DEVICE INCLUDING STORAGE CONTROLLER Dec 10, 2024 Pending
Array ( [id] => 20003379 [patent_doc_number] => 20250141601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => METHODS AND APPARATUS FOR SELECTIVE RETRANSMISSION [patent_app_type] => utility [patent_app_number] => 18/973919 [patent_app_country] => US [patent_app_date] => 2024-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22838 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18973919 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/973919
METHODS AND APPARATUS FOR SELECTIVE RETRANSMISSION Dec 8, 2024 Pending
Array ( [id] => 20051356 [patent_doc_number] => 20250189578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => ERROR DETECTION SYSTEM APPLICABLE TO RTL MODULE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/960738 [patent_app_country] => US [patent_app_date] => 2024-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18960738 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/960738
ERROR DETECTION SYSTEM APPLICABLE TO RTL MODULE AND OPERATION METHOD THEREOF Nov 25, 2024 Pending
Array ( [id] => 20740157 [patent_doc_number] => 20260149466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-28 [patent_title] => LOW-DENSITY PARITY-CHECK (LDPC) CODE GENERATION IN ASYNCHRONOUS SCRAMBLED CODED MULTIPLE ACCESS (ASCMA) TELECOMMUNICATION NETWORK [patent_app_type] => utility [patent_app_number] => 18/959368 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18959368 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/959368
LOW-DENSITY PARITY-CHECK (LDPC) CODE GENERATION IN ASYNCHRONOUS SCRAMBLED CODED MULTIPLE ACCESS (ASCMA) TELECOMMUNICATION NETWORK Nov 24, 2024 Pending
Array ( [id] => 20726025 [patent_doc_number] => 20260142745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-21 [patent_title] => BIT INTERLEAVING OF MODULATION SYMBOL MAPPING FOR DATA CARRYING REFERENCE SIGNALS [patent_app_type] => utility [patent_app_number] => 18/955768 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955768 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/955768
BIT INTERLEAVING OF MODULATION SYMBOL MAPPING FOR DATA CARRYING REFERENCE SIGNALS Nov 20, 2024 Issued
Array ( [id] => 20124291 [patent_doc_number] => 20250239322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => 3D STACK TESTING [patent_app_type] => utility [patent_app_number] => 18/951078 [patent_app_country] => US [patent_app_date] => 2024-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18951078 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/951078
3D STACK TESTING Nov 17, 2024 Pending
Array ( [id] => 19771385 [patent_doc_number] => 20250052811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES [patent_app_type] => utility [patent_app_number] => 18/929310 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18929310 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/929310
Interface to full and reduced pin JTAG devices Oct 27, 2024 Issued
Array ( [id] => 20915716 [patent_doc_number] => 12712570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-18 [patent_title] => Method and device for correcting errors in resistive memories [patent_app_type] => utility [patent_app_number] => 18/917923 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4557 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917923 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/917923
Method and device for correcting errors in resistive memories Oct 15, 2024 Pending
Array ( [id] => 19994641 [patent_doc_number] => 20250132863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => COMPUTING A POLAR TRANSFORMATION [patent_app_type] => utility [patent_app_number] => 18/917805 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 986 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917805 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/917805
COMPUTING A POLAR TRANSFORMATION Oct 15, 2024 Issued
Array ( [id] => 20061684 [patent_doc_number] => 20250199906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => METHOD AND APPARATUS FOR FLEXIBLE ON-CHIP MEMORY CONFIGURATION TO SUPPORT MULTIPLE ERROR DETECTION AND CORRECTION MECHANISMS [patent_app_type] => utility [patent_app_number] => 18/893070 [patent_app_country] => US [patent_app_date] => 2024-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18893070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/893070
METHOD AND APPARATUS FOR FLEXIBLE ON-CHIP MEMORY CONFIGURATION TO SUPPORT MULTIPLE ERROR DETECTION AND CORRECTION MECHANISMS Sep 22, 2024 Pending
Array ( [id] => 20618012 [patent_doc_number] => 20260088115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => FASTER METHOD TO PREVENT HYBRID SINGLE LEVEL CELL DEFECTS IN SYSTEM [patent_app_type] => utility [patent_app_number] => 18/891932 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18891932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/891932
FASTER METHOD TO PREVENT HYBRID SINGLE LEVEL CELL DEFECTS IN SYSTEM Sep 19, 2024 Pending
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