Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19851585 [patent_doc_number] => 20250096936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => COMMUNICATION SYSTEM, COMMUNICATION DEVICE AND COMMUNICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/882535 [patent_app_country] => US [patent_app_date] => 2024-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882535 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/882535
COMMUNICATION SYSTEM, COMMUNICATION DEVICE AND COMMUNICATION METHOD Sep 10, 2024 Pending
Array ( [id] => 19620079 [patent_doc_number] => 20240405759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => EMBEDDED PATTERN GENERATOR [patent_app_type] => utility [patent_app_number] => 18/805795 [patent_app_country] => US [patent_app_date] => 2024-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18805795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/805795
EMBEDDED PATTERN GENERATOR Aug 14, 2024 Pending
Array ( [id] => 20235533 [patent_doc_number] => 20250292852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => MEMORY DEVICE DETECTING FAIL OF THROUGH-SILICON VIA [patent_app_type] => utility [patent_app_number] => 18/798499 [patent_app_country] => US [patent_app_date] => 2024-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18798499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/798499
MEMORY DEVICE DETECTING FAIL OF THROUGH-SILICON VIA Aug 7, 2024 Pending
Array ( [id] => 19587687 [patent_doc_number] => 20240385244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => ADDRESSABLE TEST ACCESS PORT [patent_app_type] => utility [patent_app_number] => 18/786933 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786933
ADDRESSABLE TEST ACCESS PORT Jul 28, 2024 Pending
Array ( [id] => 20331603 [patent_doc_number] => 12461880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Test data transfer in multi-die systems [patent_app_type] => utility [patent_app_number] => 18/785170 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2537 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/785170
Test data transfer in multi-die systems Jul 25, 2024 Issued
Array ( [id] => 19697388 [patent_doc_number] => 20250015933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => POLAR CODE ENCODING METHOD, POLAR CODE DECODING METHOD, AND APPARATUSES THEREOF [patent_app_type] => utility [patent_app_number] => 18/779058 [patent_app_country] => US [patent_app_date] => 2024-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18779058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/779058
POLAR CODE ENCODING METHOD, POLAR CODE DECODING METHOD, AND APPARATUSES THEREOF Jul 20, 2024 Pending
Array ( [id] => 19992451 [patent_doc_number] => 20250130673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => AUTOMOTIVE TOUCH CIRCUIT DEVICE WITH ESD PROTECTION [patent_app_type] => utility [patent_app_number] => 18/776478 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776478 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776478
AUTOMOTIVE TOUCH CIRCUIT DEVICE WITH ESD PROTECTION Jul 17, 2024 Pending
Array ( [id] => 20236391 [patent_doc_number] => 20250293710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => ERROR CORRECTION CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/771392 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771392 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771392
ERROR CORRECTION CIRCUIT Jul 11, 2024 Pending
Array ( [id] => 20216592 [patent_doc_number] => 12413251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Semiconductor memory device and method of controlling the same [patent_app_type] => utility [patent_app_number] => 18/771866 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 1126 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771866
Semiconductor memory device and method of controlling the same Jul 11, 2024 Issued
Array ( [id] => 19544349 [patent_doc_number] => 20240361385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis [patent_app_type] => utility [patent_app_number] => 18/767186 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767186
Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis Jul 8, 2024 Pending
Array ( [id] => 19713528 [patent_doc_number] => 20250023670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => Low-Latency Wireless Audio System [patent_app_type] => utility [patent_app_number] => 18/763533 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763533 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763533
Low-Latency Wireless Audio System Jul 2, 2024 Pending
Array ( [id] => 19687741 [patent_doc_number] => 20250006286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => NON-LINEAR MEMORY FAILURE ANALYSIS METHOD AND MEMORY TEST APPARATUS [patent_app_type] => utility [patent_app_number] => 18/757178 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757178 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/757178
NON-LINEAR MEMORY FAILURE ANALYSIS METHOD AND MEMORY TEST APPARATUS Jun 26, 2024 Pending
Array ( [id] => 19941541 [patent_doc_number] => 12313667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Integrated circuit die test architecture [patent_app_type] => utility [patent_app_number] => 18/754683 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754683 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754683
Integrated circuit die test architecture Jun 25, 2024 Issued
Array ( [id] => 19812195 [patent_doc_number] => 12243604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-03-04 [patent_title] => Scannable memory array and a method for scanning memory [patent_app_type] => utility [patent_app_number] => 18/752634 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 74 [patent_no_of_words] => 24301 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752634 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752634
Scannable memory array and a method for scanning memory Jun 23, 2024 Issued
Array ( [id] => 19498673 [patent_doc_number] => 20240337691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER [patent_app_type] => utility [patent_app_number] => 18/744322 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744322 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744322
PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER Jun 13, 2024 Pending
Array ( [id] => 19647419 [patent_doc_number] => 20240421939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => METHOD AND SYSTEM FOR CONTEXT-BASED RETRANSMISSION OF LOST PACKETS [patent_app_type] => utility [patent_app_number] => 18/742891 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742891 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742891
METHOD AND SYSTEM FOR CONTEXT-BASED RETRANSMISSION OF LOST PACKETS Jun 12, 2024 Pending
Array ( [id] => 19659843 [patent_doc_number] => 20240426908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTING AN ELECTRONIC CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/742474 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742474 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742474
SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTING AN ELECTRONIC CIRCUIT Jun 12, 2024 Pending
Array ( [id] => 19465604 [patent_doc_number] => 20240319274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => 3D STACKED DIE TEST ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/734226 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/734226
3D stacked die test architecture Jun 4, 2024 Issued
Array ( [id] => 19469272 [patent_doc_number] => 20240322942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => BANDWIDTH UTILIZATION TECHNIQUES FOR IN-BAND REDUNDANT DATA [patent_app_type] => utility [patent_app_number] => 18/680660 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680660 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680660
Bandwidth utilization techniques for in-band redundant data May 30, 2024 Issued
Array ( [id] => 19451109 [patent_doc_number] => 20240311239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => DEFERRED ERROR CODE CORRECTION WITH IMPROVED EFFECTIVE DATA BANDWIDTH PERFORMANCE [patent_app_type] => utility [patent_app_number] => 18/679341 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679341 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679341
DEFERRED ERROR CODE CORRECTION WITH IMPROVED EFFECTIVE DATA BANDWIDTH PERFORMANCE May 29, 2024 Pending
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