Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19565866 [patent_doc_number] => 12140632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Device under test synchronization with automated test equipment check cycle [patent_app_type] => utility [patent_app_number] => 17/455237 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6404 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455237 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455237
Device under test synchronization with automated test equipment check cycle Nov 16, 2021 Issued
Array ( [id] => 18154156 [patent_doc_number] => 11567131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO [patent_app_type] => utility [patent_app_number] => 17/528372 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 45 [patent_no_of_words] => 13765 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/528372
Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO Nov 16, 2021 Issued
Array ( [id] => 19705564 [patent_doc_number] => 12199613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Semiconductor circuit including latch circuit for error correction [patent_app_type] => utility [patent_app_number] => 18/252360 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 12533 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18252360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/252360
Semiconductor circuit including latch circuit for error correction Nov 9, 2021 Issued
Array ( [id] => 17445425 [patent_doc_number] => 20220065930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY [patent_app_type] => utility [patent_app_number] => 17/522477 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522477 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522477
Test access port with address and command capability Nov 8, 2021 Issued
Array ( [id] => 18402774 [patent_doc_number] => 11664928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Multi-label offset lifting method [patent_app_type] => utility [patent_app_number] => 17/453926 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 120 [patent_no_of_words] => 9892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453926
Multi-label offset lifting method Nov 7, 2021 Issued
Array ( [id] => 18680968 [patent_doc_number] => 20230318631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => IMPROVING THE PERFORMANCE OF POLAR DECODERS USING VIRTUAL RANDOM CHANNELS [patent_app_type] => utility [patent_app_number] => 17/998292 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17998292 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/998292
IMPROVING THE PERFORMANCE OF POLAR DECODERS USING VIRTUAL RANDOM CHANNELS Nov 1, 2021 Abandoned
Array ( [id] => 17762711 [patent_doc_number] => 20220236323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => ERROR DETECTION DEVICE AND ERROR DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 17/510730 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510730
Error detection device and error detection method Oct 25, 2021 Issued
Array ( [id] => 18605938 [patent_doc_number] => 11747397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Addressable test access port apparatus [patent_app_type] => utility [patent_app_number] => 17/508750 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 44 [patent_no_of_words] => 16287 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508750 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508750
Addressable test access port apparatus Oct 21, 2021 Issued
Array ( [id] => 18330233 [patent_doc_number] => 11635465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Device and method for monitoring data and timing signals in integrated circuits [patent_app_type] => utility [patent_app_number] => 17/504139 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504139
Device and method for monitoring data and timing signals in integrated circuits Oct 17, 2021 Issued
Array ( [id] => 17580275 [patent_doc_number] => 20220137130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SELF DIAGNOSTIC APPARATUS FOR ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/496110 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496110 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496110
Self diagnostic apparatus for electronic device Oct 6, 2021 Issued
Array ( [id] => 18016149 [patent_doc_number] => 11508452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Circuit and associated chip [patent_app_type] => utility [patent_app_number] => 17/494646 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3024 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17494646 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/494646
Circuit and associated chip Oct 4, 2021 Issued
Array ( [id] => 18203462 [patent_doc_number] => 11585851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => IEEE 1149.1 interposer apparatus [patent_app_type] => utility [patent_app_number] => 17/491654 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 66 [patent_no_of_words] => 14287 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491654
IEEE 1149.1 interposer apparatus Sep 30, 2021 Issued
Array ( [id] => 19618007 [patent_doc_number] => 20240403687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SYSTEM FOR AUTONOMOUS STABILISATION OF QUANTUM STATES HAVING A PREDETERMINED PARITY FOR ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/246673 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18246673 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/246673
System for autonomous stabilisation of quantum states having a predetermined parity for error correction Sep 23, 2021 Issued
Array ( [id] => 19618007 [patent_doc_number] => 20240403687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SYSTEM FOR AUTONOMOUS STABILISATION OF QUANTUM STATES HAVING A PREDETERMINED PARITY FOR ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/246673 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18246673 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/246673
System for autonomous stabilisation of quantum states having a predetermined parity for error correction Sep 23, 2021 Issued
Array ( [id] => 19357392 [patent_doc_number] => 12057858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Method for reading and writing unreliable memories and a corresponding memory controller device and memory [patent_app_type] => utility [patent_app_number] => 17/482594 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 18506 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/482594
Method for reading and writing unreliable memories and a corresponding memory controller device and memory Sep 22, 2021 Issued
Array ( [id] => 17521515 [patent_doc_number] => 20220107364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => SELF-TEST CIRCUIT FOR AN INTEGRATED CIRCUIT, AND METHOD FOR OPERATING A SELF-TEST CIRCUIT FOR AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/480249 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480249
Self-test circuit for an integrated circuit, and method for operating a self-test circuit for an integrated circuit Sep 20, 2021 Issued
Array ( [id] => 17860952 [patent_doc_number] => 11442108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-13 [patent_title] => Isolation logic test circuit and associated test method [patent_app_type] => utility [patent_app_number] => 17/477237 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 12895 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477237 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477237
Isolation logic test circuit and associated test method Sep 15, 2021 Issued
Array ( [id] => 17316064 [patent_doc_number] => 20210405113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS [patent_app_type] => utility [patent_app_number] => 17/470500 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470500 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470500
Scan testing using scan frames with embedded commands Sep 8, 2021 Issued
Array ( [id] => 18189388 [patent_doc_number] => 11579973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Methods and systems for implementing redundancy in memory controllers [patent_app_type] => utility [patent_app_number] => 17/463340 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463340
Methods and systems for implementing redundancy in memory controllers Aug 30, 2021 Issued
Array ( [id] => 18188617 [patent_doc_number] => 11579193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Shadow access port integrated circuit [patent_app_type] => utility [patent_app_number] => 17/462572 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 38 [patent_no_of_words] => 12969 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462572
Shadow access port integrated circuit Aug 30, 2021 Issued
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