Search

Cynthia H. Britt

Examiner (ID: 10505, Phone: (571)272-3815 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2117, 2133, 2138, 2111
Total Applications
1872
Issued Applications
1708
Pending Applications
85
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19045152 [patent_doc_number] => 11934261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Flit-based parallel-forward error correction and parity [patent_app_type] => utility [patent_app_number] => 17/580408 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 20940 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580408 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580408
Flit-based parallel-forward error correction and parity Jan 19, 2022 Issued
Array ( [id] => 18479321 [patent_doc_number] => 11693055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Direct scan access JTAG [patent_app_type] => utility [patent_app_number] => 17/573761 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 13408 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573761 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573761
Direct scan access JTAG Jan 11, 2022 Issued
Array ( [id] => 17580272 [patent_doc_number] => 20220137127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => FAULT TOLERANT SYNCHRONIZER [patent_app_type] => utility [patent_app_number] => 17/573683 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17573683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/573683
Fault tolerant synchronizer Jan 11, 2022 Issued
Array ( [id] => 18940974 [patent_doc_number] => 20240036113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => TEST CIRCUIT, TEST METHOD, AND COMPUTING SYSTEM COMPRISING TEST CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/268517 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18268517 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/268517
Test circuit, test method, and computing system comprising test circuit for testing sequential circuit in pipeline stage Jan 5, 2022 Issued
Array ( [id] => 20731249 [patent_doc_number] => 12638503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => High-throughput scan architecture [patent_app_type] => utility [patent_app_number] => 18/726670 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 21218 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18726670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/726670
High-throughput scan architecture Jan 4, 2022 Issued
Array ( [id] => 18479322 [patent_doc_number] => 11693056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-07-04 [patent_title] => Scan chain for memory with reduced power consumption [patent_app_type] => utility [patent_app_number] => 17/560180 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3274 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560180
Scan chain for memory with reduced power consumption Dec 21, 2021 Issued
Array ( [id] => 17537528 [patent_doc_number] => 20220116137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD [patent_app_type] => utility [patent_app_number] => 17/556256 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556256
Transmission device, transmission method, reception device, and reception method Dec 19, 2021 Issued
Array ( [id] => 17709889 [patent_doc_number] => 20220209897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => Indexing-Based Feedback Codes and Methods of Use [patent_app_type] => utility [patent_app_number] => 17/556155 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556155 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556155
Indexing-based feedback codes and methods of use Dec 19, 2021 Issued
Array ( [id] => 17522018 [patent_doc_number] => 20220107867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => END-TO-END DATA PROTECTION FOR COMPUTE IN MEMORY (CIM)/COMPUTE NEAR MEMORY (CNM) [patent_app_type] => utility [patent_app_number] => 17/553623 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/553623
End-to-end data protection for compute in memory (CIM)/compute near memory (CNM) Dec 15, 2021 Issued
Array ( [id] => 18386158 [patent_doc_number] => 11656939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Storage cluster memory characterization [patent_app_type] => utility [patent_app_number] => 17/535152 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535152
Storage cluster memory characterization Nov 23, 2021 Issued
Array ( [id] => 19565866 [patent_doc_number] => 12140632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Device under test synchronization with automated test equipment check cycle [patent_app_type] => utility [patent_app_number] => 17/455237 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6404 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455237 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455237
Device under test synchronization with automated test equipment check cycle Nov 16, 2021 Issued
Array ( [id] => 17462380 [patent_doc_number] => 20220075685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => Data Storage System for Improving Data Throughput and Decode Capabilities [patent_app_type] => utility [patent_app_number] => 17/529189 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529189
Data storage system for improving data throughput and decode capabilities Nov 16, 2021 Issued
Array ( [id] => 18154156 [patent_doc_number] => 11567131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO [patent_app_type] => utility [patent_app_number] => 17/528372 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 45 [patent_no_of_words] => 13765 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/528372
Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO Nov 16, 2021 Issued
Array ( [id] => 19705564 [patent_doc_number] => 12199613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Semiconductor circuit including latch circuit for error correction [patent_app_type] => utility [patent_app_number] => 18/252360 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 12533 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18252360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/252360
Semiconductor circuit including latch circuit for error correction Nov 9, 2021 Issued
Array ( [id] => 17445425 [patent_doc_number] => 20220065930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY [patent_app_type] => utility [patent_app_number] => 17/522477 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522477 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522477
Test access port with address and command capability Nov 8, 2021 Issued
Array ( [id] => 18402774 [patent_doc_number] => 11664928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Multi-label offset lifting method [patent_app_type] => utility [patent_app_number] => 17/453926 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 114 [patent_figures_cnt] => 120 [patent_no_of_words] => 9892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453926
Multi-label offset lifting method Nov 7, 2021 Issued
Array ( [id] => 18680968 [patent_doc_number] => 20230318631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => IMPROVING THE PERFORMANCE OF POLAR DECODERS USING VIRTUAL RANDOM CHANNELS [patent_app_type] => utility [patent_app_number] => 17/998292 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17998292 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/998292
IMPROVING THE PERFORMANCE OF POLAR DECODERS USING VIRTUAL RANDOM CHANNELS Nov 1, 2021 Abandoned
Array ( [id] => 17762711 [patent_doc_number] => 20220236323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => ERROR DETECTION DEVICE AND ERROR DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 17/510730 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4137 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510730
Error detection device and error detection method Oct 25, 2021 Issued
Array ( [id] => 18605938 [patent_doc_number] => 11747397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Addressable test access port apparatus [patent_app_type] => utility [patent_app_number] => 17/508750 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 44 [patent_no_of_words] => 16287 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508750 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508750
Addressable test access port apparatus Oct 21, 2021 Issued
Array ( [id] => 18330233 [patent_doc_number] => 11635465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Device and method for monitoring data and timing signals in integrated circuits [patent_app_type] => utility [patent_app_number] => 17/504139 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504139
Device and method for monitoring data and timing signals in integrated circuits Oct 17, 2021 Issued
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