Cynthia H. Britt

Array ( [id] => 17580275 [patent_doc_number] => 20220137130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SELF DIAGNOSTIC APPARATUS FOR ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/496110 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18016149 [patent_doc_number] => 11508452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Circuit and associated chip [patent_app_type] => utility [patent_app_number] => 17/494646 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3024 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17494646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18203462 [patent_doc_number] => 11585851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => IEEE 1149.1 interposer apparatus [patent_app_type] => utility [patent_app_number] => 17/491654 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 66 [patent_no_of_words] => 14287 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19618007 [patent_doc_number] => 20240403687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SYSTEM FOR AUTONOMOUS STABILISATION OF QUANTUM STATES HAVING A PREDETERMINED PARITY FOR ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/246673 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18246673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19357392 [patent_doc_number] => 12057858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Method for reading and writing unreliable memories and a corresponding memory controller device and memory [patent_app_type] => utility [patent_app_number] => 17/482594 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 18506 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17482594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17521515 [patent_doc_number] => 20220107364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => SELF-TEST CIRCUIT FOR AN INTEGRATED CIRCUIT, AND METHOD FOR OPERATING A SELF-TEST CIRCUIT FOR AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/480249 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17860952 [patent_doc_number] => 11442108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-13 [patent_title] => Isolation logic test circuit and associated test method [patent_app_type] => utility [patent_app_number] => 17/477237 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 12895 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17316064 [patent_doc_number] => 20210405113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS [patent_app_type] => utility [patent_app_number] => 17/470500 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18188617 [patent_doc_number] => 11579193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Shadow access port integrated circuit [patent_app_type] => utility [patent_app_number] => 17/462572 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 38 [patent_no_of_words] => 12969 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18189388 [patent_doc_number] => 11579973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Methods and systems for implementing redundancy in memory controllers [patent_app_type] => utility [patent_app_number] => 17/463340 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18261571 [patent_doc_number] => 11609269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Device testing architecture of an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/406320 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 56 [patent_no_of_words] => 20590 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17229965 [patent_doc_number] => 20210356522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 17/388665 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18173566 [patent_doc_number] => 11573269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Test systems for executing self-testing in deployed automotive platforms [patent_app_type] => utility [patent_app_number] => 17/377245 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18316076 [patent_doc_number] => 11630151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Interface to full and reduced pin JTAG devices [patent_app_type] => utility [patent_app_number] => 17/369556 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 6209 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18454893 [patent_doc_number] => 20230196174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => ERROR MITIGATION TECHNIQUES [patent_app_type] => utility [patent_app_number] => 17/926147 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17926147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17171786 [patent_doc_number] => 20210325456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => REDUCED SIGNALING INTERFACE METHOD & APPARATUS [patent_app_type] => utility [patent_app_number] => 17/362319 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18256154 [patent_doc_number] => 20230083193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => UNCORRECTABLE MEMORY ERROR PREDICTION [patent_app_type] => utility [patent_app_number] => 17/348435 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17348435 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17247967 [patent_doc_number] => 20210367712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => ERROR RECOVERY AND POWER MANAGEMENT BETWEEN NODES OF AN INTERCONNECTION NETWORK [patent_app_type] => utility [patent_app_number] => 17/345910 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17114101 [patent_doc_number] => 20210294698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SOFT READ OPERATIONS WITH PROGRESSIVE DATA OUTPUT [patent_app_type] => utility [patent_app_number] => 17/342993 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19829276 [patent_doc_number] => 12250073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Instruction encoding-based data processing method and apparatus, and device [patent_app_type] => utility [patent_app_number] => 18/264730 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5809 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18264730 [rel_patent_id] =>[rel_patent_doc_number] =>)