Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18261571 [patent_doc_number] => 11609269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Device testing architecture of an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/406320 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 56 [patent_no_of_words] => 20590 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406320
Device testing architecture of an integrated circuit Aug 18, 2021 Issued
Array ( [id] => 17229965 [patent_doc_number] => 20210356522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 17/388665 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388665
Test compression in a JTAG daisy-chain environment Jul 28, 2021 Issued
Array ( [id] => 18173566 [patent_doc_number] => 11573269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Test systems for executing self-testing in deployed automotive platforms [patent_app_type] => utility [patent_app_number] => 17/377245 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377245 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377245
Test systems for executing self-testing in deployed automotive platforms Jul 14, 2021 Issued
Array ( [id] => 18316076 [patent_doc_number] => 11630151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Interface to full and reduced pin JTAG devices [patent_app_type] => utility [patent_app_number] => 17/369556 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 6209 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369556
Interface to full and reduced pin JTAG devices Jul 6, 2021 Issued
Array ( [id] => 18454893 [patent_doc_number] => 20230196174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => ERROR MITIGATION TECHNIQUES [patent_app_type] => utility [patent_app_number] => 17/926147 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17926147 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/926147
Error mitigation techniques Jun 30, 2021 Issued
Array ( [id] => 17171786 [patent_doc_number] => 20210325456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => REDUCED SIGNALING INTERFACE METHOD & APPARATUS [patent_app_type] => utility [patent_app_number] => 17/362319 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362319
Integrated circuit with reduced signaling interface Jun 28, 2021 Issued
Array ( [id] => 18256154 [patent_doc_number] => 20230083193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => UNCORRECTABLE MEMORY ERROR PREDICTION [patent_app_type] => utility [patent_app_number] => 17/348435 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16811 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17348435 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/348435
Uncorrectable memory error prediction Jun 14, 2021 Issued
Array ( [id] => 17247967 [patent_doc_number] => 20210367712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => ERROR RECOVERY AND POWER MANAGEMENT BETWEEN NODES OF AN INTERCONNECTION NETWORK [patent_app_type] => utility [patent_app_number] => 17/345910 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345910
Error recovery and power management between nodes of an interconnection network Jun 10, 2021 Issued
Array ( [id] => 17114101 [patent_doc_number] => 20210294698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SOFT READ OPERATIONS WITH PROGRESSIVE DATA OUTPUT [patent_app_type] => utility [patent_app_number] => 17/342993 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/342993
Soft read operations with progressive data output Jun 8, 2021 Issued
Array ( [id] => 17114101 [patent_doc_number] => 20210294698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SOFT READ OPERATIONS WITH PROGRESSIVE DATA OUTPUT [patent_app_type] => utility [patent_app_number] => 17/342993 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342993 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/342993
Soft read operations with progressive data output Jun 8, 2021 Issued
Array ( [id] => 19829276 [patent_doc_number] => 12250073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Instruction encoding-based data processing method and apparatus, and device [patent_app_type] => utility [patent_app_number] => 18/264730 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5809 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18264730 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/264730
Instruction encoding-based data processing method and apparatus, and device Jun 6, 2021 Issued
Array ( [id] => 19238346 [patent_doc_number] => 20240195541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => DYNAMIC CODE BLOCK GROUP (CBG) ALLOCATION [patent_app_type] => utility [patent_app_number] => 18/550903 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18550903 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/550903
Dynamic code block group (CBG) allocation Jun 2, 2021 Issued
Array ( [id] => 19741829 [patent_doc_number] => 12218682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Encoding method, decoding method, electronic device and storage medium [patent_app_type] => utility [patent_app_number] => 18/251659 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7350 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18251659 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/251659
Encoding method, decoding method, electronic device and storage medium May 19, 2021 Issued
Array ( [id] => 17068680 [patent_doc_number] => 20210270895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => 3D STACKED DIE TEST ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/323666 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323666 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323666
3D stacked die test architecture May 17, 2021 Issued
Array ( [id] => 18206167 [patent_doc_number] => 11588579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Interleaving based on code block groups for a wireless communication system [patent_app_type] => utility [patent_app_number] => 17/323393 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 14901 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323393
Interleaving based on code block groups for a wireless communication system May 17, 2021 Issued
Array ( [id] => 18106180 [patent_doc_number] => 11546087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Apparatus and method for encoding and decoding using polar code in wireless communication system [patent_app_type] => utility [patent_app_number] => 17/322119 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 15722 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322119 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322119
Apparatus and method for encoding and decoding using polar code in wireless communication system May 16, 2021 Issued
Array ( [id] => 18175669 [patent_doc_number] => 11575395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Semiconductor memory device and method of controlling the same [patent_app_type] => utility [patent_app_number] => 17/317280 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5784 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317280 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317280
Semiconductor memory device and method of controlling the same May 10, 2021 Issued
Array ( [id] => 19322208 [patent_doc_number] => 20240243756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => DECODING OF SERIES-CONCATENATED TURBO CODES [patent_app_type] => utility [patent_app_number] => 18/289644 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18289644 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/289644
Decoding of series-concatenated turbo codes May 6, 2021 Issued
Array ( [id] => 19322208 [patent_doc_number] => 20240243756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => DECODING OF SERIES-CONCATENATED TURBO CODES [patent_app_type] => utility [patent_app_number] => 18/289644 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18289644 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/289644
Decoding of series-concatenated turbo codes May 6, 2021 Issued
Array ( [id] => 18130213 [patent_doc_number] => 11556421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Protecting data memory in a signal processing system [patent_app_type] => utility [patent_app_number] => 17/242636 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9109 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242636 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242636
Protecting data memory in a signal processing system Apr 27, 2021 Issued
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