Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17969404 [patent_doc_number] => 11486928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Electronic circuit and corresponding method of testing electronic circuits [patent_app_type] => utility [patent_app_number] => 17/159511 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4436 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159511 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159511
Electronic circuit and corresponding method of testing electronic circuits Jan 26, 2021 Issued
Array ( [id] => 16851443 [patent_doc_number] => 20210152188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => DATA PROCESSING DEVICE AND DATA PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/158839 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 487 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158839 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158839
Data processing device and data processing method Jan 25, 2021 Issued
Array ( [id] => 17714633 [patent_doc_number] => 11378622 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-05 [patent_title] => Methods and systems for single-event upset fault injection testing [patent_app_type] => utility [patent_app_number] => 17/141872 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141872
Methods and systems for single-event upset fault injection testing Jan 4, 2021 Issued
Array ( [id] => 17940269 [patent_doc_number] => 11474722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Non-volatile memory including selective error correction [patent_app_type] => utility [patent_app_number] => 17/139526 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139526 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139526
Non-volatile memory including selective error correction Dec 30, 2020 Issued
Array ( [id] => 16917770 [patent_doc_number] => 20210190862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => SELF-TEST OF AN ASYNCHRONOUS CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/136198 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136198
Self-test of an asynchronous circuit Dec 28, 2020 Issued
Array ( [id] => 17510085 [patent_doc_number] => 20220103189 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2022-03-31 [patent_title] => ENCODING METHOD AND DEVICE, AND APPARATUS [patent_app_type] => utility [patent_app_number] => 17/135061 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135061 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135061
Encoding method and device, and apparatus Dec 27, 2020 Issued
Array ( [id] => 17510085 [patent_doc_number] => 20220103189 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2022-03-31 [patent_title] => ENCODING METHOD AND DEVICE, AND APPARATUS [patent_app_type] => utility [patent_app_number] => 17/135061 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135061 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135061
Encoding method and device, and apparatus Dec 27, 2020 Issued
Array ( [id] => 17245571 [patent_doc_number] => 20210365315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => TOPOLOGICAL QUANTUM ERROR CORRECTION USING A DATA BUS [patent_app_type] => utility [patent_app_number] => 17/135526 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135526 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135526
TOPOLOGICAL QUANTUM ERROR CORRECTION USING A DATA BUS Dec 27, 2020 Abandoned
Array ( [id] => 17689442 [patent_doc_number] => 20220196735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => DEBUG TRACE MICROSECTORS [patent_app_type] => utility [patent_app_number] => 17/132683 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132683
Debug trace microsectors Dec 22, 2020 Issued
Array ( [id] => 17691886 [patent_doc_number] => 20220199179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => WORKLOAD ADAPTIVE SCANS FOR MEMORY SUB-SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/127012 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127012 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127012
Workload adaptive scans for memory sub-systems Dec 17, 2020 Issued
Array ( [id] => 17498772 [patent_doc_number] => 11287473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Tap, command, router circuitry, and data register [patent_app_type] => utility [patent_app_number] => 17/117532 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 43 [patent_no_of_words] => 13092 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117532
Tap, command, router circuitry, and data register Dec 9, 2020 Issued
Array ( [id] => 17714634 [patent_doc_number] => 11378623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Diagnostic enhancement for multiple instances of identical structures [patent_app_type] => utility [patent_app_number] => 17/115434 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7478 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115434
Diagnostic enhancement for multiple instances of identical structures Dec 7, 2020 Issued
Array ( [id] => 16722090 [patent_doc_number] => 20210089237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => MEMORY COMPONENT HAVING INTERNAL READ-MODIFY-WRITE OPERATION [patent_app_type] => utility [patent_app_number] => 17/247167 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247167
Memory component having internal read-modify-write operation Dec 1, 2020 Issued
Array ( [id] => 18046010 [patent_doc_number] => 11519959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Reduced signaling interface circuit [patent_app_type] => utility [patent_app_number] => 16/950030 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 46 [patent_no_of_words] => 16317 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950030 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950030
Reduced signaling interface circuit Nov 16, 2020 Issued
Array ( [id] => 16848232 [patent_doc_number] => 20210148977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => SIDE-CHANNEL SIGNATURE BASED PCB AUTHENTICATION USING JTAG ARCHITECTURE AND A CHALLENGE-RESPONSE MECHANISM [patent_app_type] => utility [patent_app_number] => 17/097446 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097446
Side-channel signature based PCB authentication using JTAG architecture and a challenge-response mechanism Nov 12, 2020 Issued
Array ( [id] => 17998919 [patent_doc_number] => 11500021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Method of testing electronic circuits and corresponding circuit [patent_app_type] => utility [patent_app_number] => 17/096583 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4403 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096583 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096583
Method of testing electronic circuits and corresponding circuit Nov 11, 2020 Issued
Array ( [id] => 17893827 [patent_doc_number] => 11456820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Method and apparatus for wireless communications with unequal error protection [patent_app_type] => utility [patent_app_number] => 17/089101 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 9327 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089101 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/089101
Method and apparatus for wireless communications with unequal error protection Nov 3, 2020 Issued
Array ( [id] => 17638763 [patent_doc_number] => 11349502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Soft decoding of rate-compatible polar codes [patent_app_type] => utility [patent_app_number] => 17/088556 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13607 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/088556
Soft decoding of rate-compatible polar codes Nov 2, 2020 Issued
Array ( [id] => 17580273 [patent_doc_number] => 20220137128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => HIGH SPEED DEBUG-DELAY COMPENSATION IN EXTERNAL TOOL [patent_app_type] => utility [patent_app_number] => 17/083876 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/083876
High speed debug-delay compensation in external tool Oct 28, 2020 Issued
Array ( [id] => 16622845 [patent_doc_number] => 20210041498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY [patent_app_type] => utility [patent_app_number] => 17/077338 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077338
Test access port with address and command capability Oct 21, 2020 Issued
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