Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16615018 [patent_doc_number] => 20210033671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY [patent_app_type] => utility [patent_app_number] => 17/076576 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076576 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076576
Test access port with address and command capability Oct 20, 2020 Issued
Array ( [id] => 16622847 [patent_doc_number] => 20210041500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO [patent_app_type] => utility [patent_app_number] => 17/075015 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075015 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075015
Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO Oct 19, 2020 Issued
Array ( [id] => 17737757 [patent_doc_number] => 20220223219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => TEST METHOD FOR CONTROL CHIP AND RELATED DEVICE [patent_app_type] => utility [patent_app_number] => 17/595456 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17595456 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/595456
Test method for control chip and related device Oct 14, 2020 Issued
Array ( [id] => 18989072 [patent_doc_number] => 20240061041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => SYSTEM AND METHOD FOR ACCESS CONTROL OF A PLURALITY OF INSTRUMENTS EMBEDDED IN A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/766849 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17766849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/766849
System and method for access control of a plurality of instruments embedded in a semiconductor device Oct 8, 2020 Issued
Array ( [id] => 17534740 [patent_doc_number] => 20220113349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => ON-DIE LOGIC ANALYZER [patent_app_type] => utility [patent_app_number] => 17/067288 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067288 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067288
On-die logic analyzer Oct 8, 2020 Issued
Array ( [id] => 17728904 [patent_doc_number] => 11385288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Device, method and system of error detection and correction in multiple devices [patent_app_type] => utility [patent_app_number] => 17/031716 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3914 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031716
Device, method and system of error detection and correction in multiple devices Sep 23, 2020 Issued
Array ( [id] => 17650785 [patent_doc_number] => 11353508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Method, system and device to test a plurality of devices by comparing test results of test chains of the plurality of devices [patent_app_type] => utility [patent_app_number] => 17/031713 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4122 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031713 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031713
Method, system and device to test a plurality of devices by comparing test results of test chains of the plurality of devices Sep 23, 2020 Issued
Array ( [id] => 16559140 [patent_doc_number] => 20210004289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, MEMORY SYSTEM, AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/029912 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029912 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029912
Semiconductor memory device, controller, memory system, and operation method thereof Sep 22, 2020 Issued
Array ( [id] => 16729033 [patent_doc_number] => 20210096180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => CHIP AND TESTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/028021 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028021 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028021
Chip and testing method thereof Sep 21, 2020 Issued
Array ( [id] => 17588853 [patent_doc_number] => 11327115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Scheme applied in JTAG TAP apparatus, JTAG host, and target system capable of achieving data verification as well as saving on-chip circuit costs [patent_app_type] => utility [patent_app_number] => 17/029000 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4612 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029000
Scheme applied in JTAG TAP apparatus, JTAG host, and target system capable of achieving data verification as well as saving on-chip circuit costs Sep 21, 2020 Issued
Array ( [id] => 18046014 [patent_doc_number] => 11519963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Semiconductor integrated circuit having scan chains sequentially supplied with a clock signal [patent_app_type] => utility [patent_app_number] => 17/019668 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 4925 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019668 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/019668
Semiconductor integrated circuit having scan chains sequentially supplied with a clock signal Sep 13, 2020 Issued
Array ( [id] => 17113285 [patent_doc_number] => 20210293882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/017772 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017772 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017772
Semiconductor device for controlling supply of clock signal Sep 10, 2020 Issued
Array ( [id] => 17076066 [patent_doc_number] => 11112458 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-07 [patent_title] => Testing an integrated circuit having conservative reversible logic [patent_app_type] => utility [patent_app_number] => 16/999419 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999419 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999419
Testing an integrated circuit having conservative reversible logic Aug 20, 2020 Issued
Array ( [id] => 17394245 [patent_doc_number] => 11243252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-08 [patent_title] => Processor to JTAG test data register interface [patent_app_type] => utility [patent_app_number] => 16/995179 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16995179 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/995179
Processor to JTAG test data register interface Aug 16, 2020 Issued
Array ( [id] => 16425814 [patent_doc_number] => 20200351012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD [patent_app_type] => utility [patent_app_number] => 16/932968 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/932968
Transmission device, transmission method, reception device, and reception method Jul 19, 2020 Issued
Array ( [id] => 16403141 [patent_doc_number] => 20200343999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => SOFT FEC WITH PARITY CHECK [patent_app_type] => utility [patent_app_number] => 16/928821 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928821 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/928821
Soft FEC with parity check Jul 13, 2020 Issued
Array ( [id] => 17785818 [patent_doc_number] => 11408936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Generating multiple pseudo static control signals using on-chip JTAG state machine [patent_app_type] => utility [patent_app_number] => 16/920806 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7948 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/920806
Generating multiple pseudo static control signals using on-chip JTAG state machine Jul 5, 2020 Issued
Array ( [id] => 16993312 [patent_doc_number] => 20210231732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => SEMICONDUCTOR DEVICE HAVING MICRO-BUMPS AND TEST METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/918926 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16918926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/918926
Semiconductor device having micro-bumps and test method thereof Jun 30, 2020 Issued
Array ( [id] => 19199679 [patent_doc_number] => 11996937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Encoding device, encoding method, decoding device, decoding method, and program [patent_app_type] => utility [patent_app_number] => 17/636989 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 64 [patent_no_of_words] => 47184 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17636989 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/636989
Encoding device, encoding method, decoding device, decoding method, and program Jun 29, 2020 Issued
Array ( [id] => 16363212 [patent_doc_number] => 20200319963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => Data Storage System for Improving Data Throughput and Decode Capabilities [patent_app_type] => utility [patent_app_number] => 16/905796 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905796 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905796
Data storage system for improving data throughput and decode capabilities Jun 17, 2020 Issued
Menu