
Cynthia H. Britt
Examiner (ID: 11869)
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2117, 2111, 2133, 2138 |
| Total Applications | 1844 |
| Issued Applications | 1687 |
| Pending Applications | 80 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16363219
[patent_doc_number] => 20200319970
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-08
[patent_title] => SOFT CHIP-KILL RECOVERY FOR MULTIPLE WORDLINES FAILURE
[patent_app_type] => utility
[patent_app_number] => 16/905787
[patent_app_country] => US
[patent_app_date] => 2020-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9746
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905787
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/905787 | Soft chip-kill recovery for multiple wordlines failure | Jun 17, 2020 | Issued |
Array
(
[id] => 17222844
[patent_doc_number] => 11175339
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-16
[patent_title] => IC analog boundary scan cell, digital cell, comparator, analog switches
[patent_app_type] => utility
[patent_app_number] => 16/904142
[patent_app_country] => US
[patent_app_date] => 2020-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 66
[patent_no_of_words] => 14273
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16904142
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/904142 | IC analog boundary scan cell, digital cell, comparator, analog switches | Jun 16, 2020 | Issued |
Array
(
[id] => 16546065
[patent_doc_number] => 20200412480
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-31
[patent_title] => Multi-Label Offset Lifting Method
[patent_app_type] => utility
[patent_app_number] => 16/899248
[patent_app_country] => US
[patent_app_date] => 2020-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9850
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899248
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/899248 | Multi-label offset lifting method | Jun 10, 2020 | Issued |
Array
(
[id] => 16314679
[patent_doc_number] => 20200293417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-17
[patent_title] => SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/888013
[patent_app_country] => US
[patent_app_date] => 2020-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9693
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888013
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/888013 | Scan synchronous-write-through testing architectures for a memory device | May 28, 2020 | Issued |
Array
(
[id] => 17151618
[patent_doc_number] => 11144696
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-10-12
[patent_title] => Low cost design for test architecture
[patent_app_type] => utility
[patent_app_number] => 16/884042
[patent_app_country] => US
[patent_app_date] => 2020-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 60
[patent_no_of_words] => 37805
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884042
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/884042 | Low cost design for test architecture | May 26, 2020 | Issued |
Array
(
[id] => 16929013
[patent_doc_number] => 11050514
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-06-29
[patent_title] => Error recovery and power management between nodes of an interconnection network
[patent_app_type] => utility
[patent_app_number] => 16/880018
[patent_app_country] => US
[patent_app_date] => 2020-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 21
[patent_no_of_words] => 15137
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880018
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/880018 | Error recovery and power management between nodes of an interconnection network | May 20, 2020 | Issued |
Array
(
[id] => 16284788
[patent_doc_number] => 20200278390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-03
[patent_title] => INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFFCHIP TAP INTERFACE PORT
[patent_app_type] => utility
[patent_app_number] => 16/875539
[patent_app_country] => US
[patent_app_date] => 2020-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5793
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16875539
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/875539 | Integrated circuit with JTAG port, tap linking module, and off-chip TAP interface port | May 14, 2020 | Issued |
Array
(
[id] => 16254859
[patent_doc_number] => 20200264233
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-20
[patent_title] => PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO
[patent_app_type] => utility
[patent_app_number] => 16/869181
[patent_app_country] => US
[patent_app_date] => 2020-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13742
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869181
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/869181 | Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO | May 6, 2020 | Issued |
Array
(
[id] => 16438417
[patent_doc_number] => 20200355743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-12
[patent_title] => METHOD AND DEVICE FOR SENDING DATA ACCORDING TO A SIGNAL TIMING
[patent_app_type] => utility
[patent_app_number] => 16/867884
[patent_app_country] => US
[patent_app_date] => 2020-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8935
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16867884
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/867884 | Method and device for sending data according to a signal timing | May 5, 2020 | Issued |
Array
(
[id] => 17543912
[patent_doc_number] => 11309044
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-19
[patent_title] => Test circuit for testing a storage circuit
[patent_app_type] => utility
[patent_app_number] => 16/847010
[patent_app_country] => US
[patent_app_date] => 2020-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6000
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847010
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/847010 | Test circuit for testing a storage circuit | Apr 12, 2020 | Issued |
Array
(
[id] => 17158794
[patent_doc_number] => 20210319845
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-14
[patent_title] => MICROCHIP LEVEL SHARED ARRAY REPAIR
[patent_app_type] => utility
[patent_app_number] => 16/845259
[patent_app_country] => US
[patent_app_date] => 2020-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5335
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845259
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/845259 | Microchip level shared array repair | Apr 9, 2020 | Issued |
Array
(
[id] => 17422461
[patent_doc_number] => 11255908
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-22
[patent_title] => Direct scan access JTAG
[patent_app_type] => utility
[patent_app_number] => 16/843535
[patent_app_country] => US
[patent_app_date] => 2020-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 35
[patent_no_of_words] => 13384
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843535
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/843535 | Direct scan access JTAG | Apr 7, 2020 | Issued |
Array
(
[id] => 17061256
[patent_doc_number] => 11105852
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-31
[patent_title] => Test compression in a JTAG daisy-chain environment
[patent_app_type] => utility
[patent_app_number] => 16/825434
[patent_app_country] => US
[patent_app_date] => 2020-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 51
[patent_no_of_words] => 14392
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 526
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825434
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/825434 | Test compression in a JTAG daisy-chain environment | Mar 19, 2020 | Issued |
Array
(
[id] => 16164853
[patent_doc_number] => 20200220659
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-09
[patent_title] => SOFT FEC WITH PARITY CHECK
[patent_app_type] => utility
[patent_app_number] => 16/824261
[patent_app_country] => US
[patent_app_date] => 2020-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7428
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824261
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/824261 | Soft FEC with parity check | Mar 18, 2020 | Issued |
Array
(
[id] => 16159313
[patent_doc_number] => 20200217889
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-09
[patent_title] => SHADOW ACCESS PORT METHOD AND APPARATUS
[patent_app_type] => utility
[patent_app_number] => 16/824371
[patent_app_country] => US
[patent_app_date] => 2020-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12948
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824371
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/824371 | TAP,TCK inverter,shadow access port scan/instruction registers,state machine | Mar 18, 2020 | Issued |
Array
(
[id] => 17564479
[patent_doc_number] => 20220128628
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => SINGLE-PASS DIAGNOSIS FOR MULTIPLE CHAIN DEFECTS
[patent_app_type] => utility
[patent_app_number] => 17/438521
[patent_app_country] => US
[patent_app_date] => 2020-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12264
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17438521
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/438521 | Single-pass diagnosis for multiple chain defects | Mar 12, 2020 | Issued |
Array
(
[id] => 17121121
[patent_doc_number] => 11132255
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-28
[patent_title] => Methods and systems for implementing redundancy in memory controllers
[patent_app_type] => utility
[patent_app_number] => 16/818949
[patent_app_country] => US
[patent_app_date] => 2020-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7279
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818949
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/818949 | Methods and systems for implementing redundancy in memory controllers | Mar 12, 2020 | Issued |
Array
(
[id] => 16116509
[patent_doc_number] => 20200210277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => DATA STORAGE DEVICE EMPLOYING MULTI-LEVEL PARITY SECTORS FOR DATA RECOVERY PROCEDURE
[patent_app_type] => utility
[patent_app_number] => 16/815416
[patent_app_country] => US
[patent_app_date] => 2020-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7997
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16815416
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/815416 | Data storage device employing multi-level parity sectors for data recovery procedure | Mar 10, 2020 | Issued |
Array
(
[id] => 17061257
[patent_doc_number] => 11105853
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-08-31
[patent_title] => Empirical LBIST latch switching and state probability determination
[patent_app_type] => utility
[patent_app_number] => 16/804073
[patent_app_country] => US
[patent_app_date] => 2020-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9607
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16804073
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/804073 | Empirical LBIST latch switching and state probability determination | Feb 27, 2020 | Issued |
Array
(
[id] => 17491533
[patent_doc_number] => 11280831
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-22
[patent_title] => Semiconductor integrated circuit with self testing and method of testing
[patent_app_type] => utility
[patent_app_number] => 16/800288
[patent_app_country] => US
[patent_app_date] => 2020-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 18
[patent_no_of_words] => 5611
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800288
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/800288 | Semiconductor integrated circuit with self testing and method of testing | Feb 24, 2020 | Issued |