Search

Cynthia H. Britt

Examiner (ID: 10505, Phone: (571)272-3815 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2117, 2133, 2138, 2111
Total Applications
1872
Issued Applications
1708
Pending Applications
85
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17076066 [patent_doc_number] => 11112458 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-07 [patent_title] => Testing an integrated circuit having conservative reversible logic [patent_app_type] => utility [patent_app_number] => 16/999419 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999419 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999419
Testing an integrated circuit having conservative reversible logic Aug 20, 2020 Issued
Array ( [id] => 17394245 [patent_doc_number] => 11243252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-08 [patent_title] => Processor to JTAG test data register interface [patent_app_type] => utility [patent_app_number] => 16/995179 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16995179 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/995179
Processor to JTAG test data register interface Aug 16, 2020 Issued
Array ( [id] => 16425814 [patent_doc_number] => 20200351012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD [patent_app_type] => utility [patent_app_number] => 16/932968 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/932968
Transmission device, transmission method, reception device, and reception method Jul 19, 2020 Issued
Array ( [id] => 16403141 [patent_doc_number] => 20200343999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => SOFT FEC WITH PARITY CHECK [patent_app_type] => utility [patent_app_number] => 16/928821 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16928821 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/928821
Soft FEC with parity check Jul 13, 2020 Issued
Array ( [id] => 17785818 [patent_doc_number] => 11408936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Generating multiple pseudo static control signals using on-chip JTAG state machine [patent_app_type] => utility [patent_app_number] => 16/920806 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7948 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/920806
Generating multiple pseudo static control signals using on-chip JTAG state machine Jul 5, 2020 Issued
Array ( [id] => 16993312 [patent_doc_number] => 20210231732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => SEMICONDUCTOR DEVICE HAVING MICRO-BUMPS AND TEST METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/918926 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16918926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/918926
Semiconductor device having micro-bumps and test method thereof Jun 30, 2020 Issued
Array ( [id] => 19199679 [patent_doc_number] => 11996937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Encoding device, encoding method, decoding device, decoding method, and program [patent_app_type] => utility [patent_app_number] => 17/636989 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 64 [patent_no_of_words] => 47184 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17636989 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/636989
Encoding device, encoding method, decoding device, decoding method, and program Jun 29, 2020 Issued
Array ( [id] => 16363212 [patent_doc_number] => 20200319963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => Data Storage System for Improving Data Throughput and Decode Capabilities [patent_app_type] => utility [patent_app_number] => 16/905796 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905796 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905796
Data storage system for improving data throughput and decode capabilities Jun 17, 2020 Issued
Array ( [id] => 16363219 [patent_doc_number] => 20200319970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => SOFT CHIP-KILL RECOVERY FOR MULTIPLE WORDLINES FAILURE [patent_app_type] => utility [patent_app_number] => 16/905787 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905787 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905787
Soft chip-kill recovery for multiple wordlines failure Jun 17, 2020 Issued
Array ( [id] => 17222844 [patent_doc_number] => 11175339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => IC analog boundary scan cell, digital cell, comparator, analog switches [patent_app_type] => utility [patent_app_number] => 16/904142 [patent_app_country] => US [patent_app_date] => 2020-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 66 [patent_no_of_words] => 14273 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16904142 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/904142
IC analog boundary scan cell, digital cell, comparator, analog switches Jun 16, 2020 Issued
Array ( [id] => 16546065 [patent_doc_number] => 20200412480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => Multi-Label Offset Lifting Method [patent_app_type] => utility [patent_app_number] => 16/899248 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899248 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899248
Multi-label offset lifting method Jun 10, 2020 Issued
Array ( [id] => 16314679 [patent_doc_number] => 20200293417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/888013 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888013 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/888013
Scan synchronous-write-through testing architectures for a memory device May 28, 2020 Issued
Array ( [id] => 17151618 [patent_doc_number] => 11144696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-12 [patent_title] => Low cost design for test architecture [patent_app_type] => utility [patent_app_number] => 16/884042 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 60 [patent_no_of_words] => 37805 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/884042
Low cost design for test architecture May 26, 2020 Issued
Array ( [id] => 16929013 [patent_doc_number] => 11050514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-29 [patent_title] => Error recovery and power management between nodes of an interconnection network [patent_app_type] => utility [patent_app_number] => 16/880018 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 15137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880018 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/880018
Error recovery and power management between nodes of an interconnection network May 20, 2020 Issued
Array ( [id] => 16284788 [patent_doc_number] => 20200278390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFFCHIP TAP INTERFACE PORT [patent_app_type] => utility [patent_app_number] => 16/875539 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16875539 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/875539
Integrated circuit with JTAG port, tap linking module, and off-chip TAP interface port May 14, 2020 Issued
Array ( [id] => 16254859 [patent_doc_number] => 20200264233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO [patent_app_type] => utility [patent_app_number] => 16/869181 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869181 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/869181
Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO May 6, 2020 Issued
Array ( [id] => 16438417 [patent_doc_number] => 20200355743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => METHOD AND DEVICE FOR SENDING DATA ACCORDING TO A SIGNAL TIMING [patent_app_type] => utility [patent_app_number] => 16/867884 [patent_app_country] => US [patent_app_date] => 2020-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16867884 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/867884
Method and device for sending data according to a signal timing May 5, 2020 Issued
Array ( [id] => 17543912 [patent_doc_number] => 11309044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Test circuit for testing a storage circuit [patent_app_type] => utility [patent_app_number] => 16/847010 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847010 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/847010
Test circuit for testing a storage circuit Apr 12, 2020 Issued
Array ( [id] => 17158794 [patent_doc_number] => 20210319845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => MICROCHIP LEVEL SHARED ARRAY REPAIR [patent_app_type] => utility [patent_app_number] => 16/845259 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845259 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845259
Microchip level shared array repair Apr 9, 2020 Issued
Array ( [id] => 17422461 [patent_doc_number] => 11255908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Direct scan access JTAG [patent_app_type] => utility [patent_app_number] => 16/843535 [patent_app_country] => US [patent_app_date] => 2020-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 13384 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843535 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/843535
Direct scan access JTAG Apr 7, 2020 Issued
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