Search

Cynthia H. Britt

Examiner (ID: 10505, Phone: (571)272-3815 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2117, 2133, 2138, 2111
Total Applications
1872
Issued Applications
1708
Pending Applications
85
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17061256 [patent_doc_number] => 11105852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Test compression in a JTAG daisy-chain environment [patent_app_type] => utility [patent_app_number] => 16/825434 [patent_app_country] => US [patent_app_date] => 2020-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 51 [patent_no_of_words] => 14392 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 526 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16825434 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/825434
Test compression in a JTAG daisy-chain environment Mar 19, 2020 Issued
Array ( [id] => 16159313 [patent_doc_number] => 20200217889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => SHADOW ACCESS PORT METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 16/824371 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824371 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/824371
TAP,TCK inverter,shadow access port scan/instruction registers,state machine Mar 18, 2020 Issued
Array ( [id] => 16164853 [patent_doc_number] => 20200220659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => SOFT FEC WITH PARITY CHECK [patent_app_type] => utility [patent_app_number] => 16/824261 [patent_app_country] => US [patent_app_date] => 2020-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824261 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/824261
Soft FEC with parity check Mar 18, 2020 Issued
Array ( [id] => 17564479 [patent_doc_number] => 20220128628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => SINGLE-PASS DIAGNOSIS FOR MULTIPLE CHAIN DEFECTS [patent_app_type] => utility [patent_app_number] => 17/438521 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17438521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/438521
Single-pass diagnosis for multiple chain defects Mar 12, 2020 Issued
Array ( [id] => 17121121 [patent_doc_number] => 11132255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Methods and systems for implementing redundancy in memory controllers [patent_app_type] => utility [patent_app_number] => 16/818949 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818949 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/818949
Methods and systems for implementing redundancy in memory controllers Mar 12, 2020 Issued
Array ( [id] => 16116509 [patent_doc_number] => 20200210277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => DATA STORAGE DEVICE EMPLOYING MULTI-LEVEL PARITY SECTORS FOR DATA RECOVERY PROCEDURE [patent_app_type] => utility [patent_app_number] => 16/815416 [patent_app_country] => US [patent_app_date] => 2020-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16815416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/815416
Data storage device employing multi-level parity sectors for data recovery procedure Mar 10, 2020 Issued
Array ( [id] => 17061257 [patent_doc_number] => 11105853 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-31 [patent_title] => Empirical LBIST latch switching and state probability determination [patent_app_type] => utility [patent_app_number] => 16/804073 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9607 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16804073 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/804073
Empirical LBIST latch switching and state probability determination Feb 27, 2020 Issued
Array ( [id] => 17491533 [patent_doc_number] => 11280831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Semiconductor integrated circuit with self testing and method of testing [patent_app_type] => utility [patent_app_number] => 16/800288 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 5611 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800288 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/800288
Semiconductor integrated circuit with self testing and method of testing Feb 24, 2020 Issued
Array ( [id] => 16077539 [patent_doc_number] => 20200192756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => Die-Level Monitoring in a Storage Cluster [patent_app_type] => utility [patent_app_number] => 16/800669 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/800669
Die-level monitoring in a storage cluster Feb 24, 2020 Issued
Array ( [id] => 16736950 [patent_doc_number] => 10962589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Stacked die interposer monitor trigger, address comparator, trigger controller circuitry [patent_app_type] => utility [patent_app_number] => 16/795825 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 50 [patent_no_of_words] => 11396 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16795825 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/795825
Stacked die interposer monitor trigger, address comparator, trigger controller circuitry Feb 19, 2020 Issued
Array ( [id] => 16016175 [patent_doc_number] => 20200182931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM [patent_app_type] => utility [patent_app_number] => 16/795262 [patent_app_country] => US [patent_app_date] => 2020-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16795262 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/795262
Test access mechanism controller including instruction register, instruction decode circuitry Feb 18, 2020 Issued
Array ( [id] => 15998027 [patent_doc_number] => 20200174884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => Protecting Data Memory in a Signal Processing System [patent_app_type] => utility [patent_app_number] => 16/788004 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788004 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/788004
Protecting data memory in a signal processing system Feb 10, 2020 Issued
Array ( [id] => 17515614 [patent_doc_number] => 11294764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Method of correcting errors in a memory array and method of screening weak bits in the same [patent_app_type] => utility [patent_app_number] => 16/786795 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786795 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786795
Method of correcting errors in a memory array and method of screening weak bits in the same Feb 9, 2020 Issued
Array ( [id] => 17590511 [patent_doc_number] => 11328786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Memory module storing test pattern information, computer system comprising the same, and test method thereof [patent_app_type] => utility [patent_app_number] => 16/781184 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16781184 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/781184
Memory module storing test pattern information, computer system comprising the same, and test method thereof Feb 3, 2020 Issued
Array ( [id] => 17108051 [patent_doc_number] => 11128282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Safety mechanism for digital reset state [patent_app_type] => utility [patent_app_number] => 16/780324 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780324 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/780324
Safety mechanism for digital reset state Feb 2, 2020 Issued
Array ( [id] => 17135896 [patent_doc_number] => 11137447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => IC test architecture having differential data input and output buffers [patent_app_type] => utility [patent_app_number] => 16/780088 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 9646 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780088 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/780088
IC test architecture having differential data input and output buffers Feb 2, 2020 Issued
Array ( [id] => 19078439 [patent_doc_number] => 11947807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Method and device for processing data stored in a memory unit [patent_app_type] => utility [patent_app_number] => 17/311227 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 15034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17311227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/311227
Method and device for processing data stored in a memory unit Jan 29, 2020 Issued
Array ( [id] => 18275547 [patent_doc_number] => 11614487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Multi-capture at-speed scan test based on a slow clock signal [patent_app_type] => utility [patent_app_number] => 17/311868 [patent_app_country] => US [patent_app_date] => 2020-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17311868 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/311868
Multi-capture at-speed scan test based on a slow clock signal Jan 27, 2020 Issued
Array ( [id] => 17517650 [patent_doc_number] => 11296820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Signaling coding and modulation method and demodulation and decoding method and device [patent_app_type] => utility [patent_app_number] => 16/748739 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8537 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/748739
Signaling coding and modulation method and demodulation and decoding method and device Jan 20, 2020 Issued
Array ( [id] => 17408254 [patent_doc_number] => 11249133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Determination of the dispersion of an electronic component [patent_app_type] => utility [patent_app_number] => 16/745813 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745813 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/745813
Determination of the dispersion of an electronic component Jan 16, 2020 Issued
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