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Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16077539 [patent_doc_number] => 20200192756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => Die-Level Monitoring in a Storage Cluster [patent_app_type] => utility [patent_app_number] => 16/800669 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/800669
Die-level monitoring in a storage cluster Feb 24, 2020 Issued
Array ( [id] => 16736950 [patent_doc_number] => 10962589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Stacked die interposer monitor trigger, address comparator, trigger controller circuitry [patent_app_type] => utility [patent_app_number] => 16/795825 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 50 [patent_no_of_words] => 11396 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16795825 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/795825
Stacked die interposer monitor trigger, address comparator, trigger controller circuitry Feb 19, 2020 Issued
Array ( [id] => 16016175 [patent_doc_number] => 20200182931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM [patent_app_type] => utility [patent_app_number] => 16/795262 [patent_app_country] => US [patent_app_date] => 2020-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16795262 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/795262
Test access mechanism controller including instruction register, instruction decode circuitry Feb 18, 2020 Issued
Array ( [id] => 15998027 [patent_doc_number] => 20200174884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => Protecting Data Memory in a Signal Processing System [patent_app_type] => utility [patent_app_number] => 16/788004 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788004 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/788004
Protecting data memory in a signal processing system Feb 10, 2020 Issued
Array ( [id] => 17515614 [patent_doc_number] => 11294764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Method of correcting errors in a memory array and method of screening weak bits in the same [patent_app_type] => utility [patent_app_number] => 16/786795 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786795 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786795
Method of correcting errors in a memory array and method of screening weak bits in the same Feb 9, 2020 Issued
Array ( [id] => 17590511 [patent_doc_number] => 11328786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Memory module storing test pattern information, computer system comprising the same, and test method thereof [patent_app_type] => utility [patent_app_number] => 16/781184 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16781184 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/781184
Memory module storing test pattern information, computer system comprising the same, and test method thereof Feb 3, 2020 Issued
Array ( [id] => 17108051 [patent_doc_number] => 11128282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Safety mechanism for digital reset state [patent_app_type] => utility [patent_app_number] => 16/780324 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780324 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/780324
Safety mechanism for digital reset state Feb 2, 2020 Issued
Array ( [id] => 17135896 [patent_doc_number] => 11137447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => IC test architecture having differential data input and output buffers [patent_app_type] => utility [patent_app_number] => 16/780088 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 9646 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780088 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/780088
IC test architecture having differential data input and output buffers Feb 2, 2020 Issued
Array ( [id] => 19078439 [patent_doc_number] => 11947807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Method and device for processing data stored in a memory unit [patent_app_type] => utility [patent_app_number] => 17/311227 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 15034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17311227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/311227
Method and device for processing data stored in a memory unit Jan 29, 2020 Issued
Array ( [id] => 18275547 [patent_doc_number] => 11614487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Multi-capture at-speed scan test based on a slow clock signal [patent_app_type] => utility [patent_app_number] => 17/311868 [patent_app_country] => US [patent_app_date] => 2020-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17311868 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/311868
Multi-capture at-speed scan test based on a slow clock signal Jan 27, 2020 Issued
Array ( [id] => 17517650 [patent_doc_number] => 11296820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Signaling coding and modulation method and demodulation and decoding method and device [patent_app_type] => utility [patent_app_number] => 16/748739 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8537 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/748739
Signaling coding and modulation method and demodulation and decoding method and device Jan 20, 2020 Issued
Array ( [id] => 17408254 [patent_doc_number] => 11249133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Determination of the dispersion of an electronic component [patent_app_type] => utility [patent_app_number] => 16/745813 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745813 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/745813
Determination of the dispersion of an electronic component Jan 16, 2020 Issued
Array ( [id] => 19295083 [patent_doc_number] => 12034453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Protocol data unit (PDU) error probability feedback [patent_app_type] => utility [patent_app_number] => 17/780768 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10479 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17780768 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/780768
Protocol data unit (PDU) error probability feedback Dec 18, 2019 Issued
Array ( [id] => 16926437 [patent_doc_number] => 11047912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => IC first/second surfaces contact points, test control port, parallel scan [patent_app_type] => utility [patent_app_number] => 16/718453 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 7068 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16718453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/718453
IC first/second surfaces contact points, test control port, parallel scan Dec 17, 2019 Issued
Array ( [id] => 15771523 [patent_doc_number] => 20200116779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => DIE STACK TEST ARCHITECTURE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/713938 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713938 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713938
Two die sides with PTI. PTO. TDI, TCK, TMS, TDO, PTIO contact points method Dec 12, 2019 Issued
Array ( [id] => 15965639 [patent_doc_number] => 20200166571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => Chain Testing And Diagnosis Using Two-Dimensional Scan Architecture [patent_app_type] => utility [patent_app_number] => 16/695322 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695322
Chain testing and diagnosis using two-dimensional scan architecture Nov 25, 2019 Issued
Array ( [id] => 16856165 [patent_doc_number] => 20210156910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => DYNAMIC WEIGHT SELECTION PROCESS FOR LOGIC BUILT-IN SELF TEST [patent_app_type] => utility [patent_app_number] => 16/693426 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16693426 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/693426
Dynamic weight selection process for logic built-in self test Nov 24, 2019 Issued
Array ( [id] => 17636164 [patent_doc_number] => 11346884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Signal analysis method and measurement instrument [patent_app_type] => utility [patent_app_number] => 16/693185 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16693185 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/693185
Signal analysis method and measurement instrument Nov 21, 2019 Issued
Array ( [id] => 15965637 [patent_doc_number] => 20200166570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => AT-SPEED TEST ACCESS PORT OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/689764 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689764
At-speed test access port operations Nov 19, 2019 Issued
Array ( [id] => 15901321 [patent_doc_number] => 20200150179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => MULTIBIT VECTORED SEQUENTIAL WITH SCAN [patent_app_type] => utility [patent_app_number] => 16/681691 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681691 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681691
Multibit vectored sequential with scan Nov 11, 2019 Issued
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