Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16744452 [patent_doc_number] => 10969432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => System-on-chip for at-speed test of logic circuit and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/544160 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11192 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16544160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/544160
System-on-chip for at-speed test of logic circuit and operating method thereof Aug 18, 2019 Issued
Array ( [id] => 16819697 [patent_doc_number] => 11004534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Preemptive read refresh in memories with time-varying error rates [patent_app_type] => utility [patent_app_number] => 16/533498 [patent_app_country] => US [patent_app_date] => 2019-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533498 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/533498
Preemptive read refresh in memories with time-varying error rates Aug 5, 2019 Issued
Array ( [id] => 16747121 [patent_doc_number] => 10972130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Encoding method, decoding method, encoding apparatus, and decoding apparatus [patent_app_type] => utility [patent_app_number] => 16/521605 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 13830 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521605 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521605
Encoding method, decoding method, encoding apparatus, and decoding apparatus Jul 24, 2019 Issued
Array ( [id] => 16697947 [patent_doc_number] => 10948539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Access ports, port selector with enable outputs, and TDI/TDO multiplexer [patent_app_type] => utility [patent_app_number] => 16/522174 [patent_app_country] => US [patent_app_date] => 2019-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 58 [patent_no_of_words] => 17538 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522174 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/522174
Access ports, port selector with enable outputs, and TDI/TDO multiplexer Jul 24, 2019 Issued
Array ( [id] => 16684935 [patent_doc_number] => 10944431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Data processing device and data processing method for improving data transmission quality using a low density parity check code [patent_app_type] => utility [patent_app_number] => 16/511971 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 220 [patent_figures_cnt] => 220 [patent_no_of_words] => 53318 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 481 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/511971
Data processing device and data processing method for improving data transmission quality using a low density parity check code Jul 14, 2019 Issued
Array ( [id] => 16820654 [patent_doc_number] => 11005500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Data processing apparatus, data processing method, and program with bit interleaving for non-uniform constellation wireless transmission [patent_app_type] => utility [patent_app_number] => 16/510059 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16510059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/510059
Data processing apparatus, data processing method, and program with bit interleaving for non-uniform constellation wireless transmission Jul 11, 2019 Issued
Array ( [id] => 17237703 [patent_doc_number] => 11181578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Operating addressable circuit inputting separate data/address signals from data input apparatus [patent_app_type] => utility [patent_app_number] => 16/508743 [patent_app_country] => US [patent_app_date] => 2019-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 44 [patent_no_of_words] => 16274 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16508743 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/508743
Operating addressable circuit inputting separate data/address signals from data input apparatus Jul 10, 2019 Issued
Array ( [id] => 16544712 [patent_doc_number] => 20200411127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => MANAGED-NAND REAL TIME ANALYZER AND METHOD [patent_app_type] => utility [patent_app_number] => 16/453712 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453712 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453712
Managed-NAND real time analyzer and method Jun 25, 2019 Issued
Array ( [id] => 16527398 [patent_doc_number] => 20200401478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => TOPOLOGICAL QUANTUM ERROR CORRECTION USING A DATA BUS [patent_app_type] => utility [patent_app_number] => 16/451713 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16451713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/451713
Topological quantum error correction using a data bus Jun 24, 2019 Issued
Array ( [id] => 15001379 [patent_doc_number] => 20190319647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => SOFT DECODING OF RATE-COMPATIBLE POLAR CODES [patent_app_type] => utility [patent_app_number] => 16/452495 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452495 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/452495
Soft decoding of rate-compatible polar codes Jun 24, 2019 Issued
Array ( [id] => 14968525 [patent_doc_number] => 20190311741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => EFFICIENT REWRITE USING LARGER CODEWORD SIZES [patent_app_type] => utility [patent_app_number] => 16/450814 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450814 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/450814
Efficient rewrite using larger codeword sizes Jun 23, 2019 Issued
Array ( [id] => 17186442 [patent_doc_number] => 20210333327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => CONTROLLER FOR A MEMORY COMPONENT [patent_app_type] => utility [patent_app_number] => 16/624948 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16624948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/624948
Controller for a memory component May 30, 2019 Issued
Array ( [id] => 17785817 [patent_doc_number] => 11408935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => JTAG registers with concurrent inputs [patent_app_type] => utility [patent_app_number] => 16/624829 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16624829 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/624829
JTAG registers with concurrent inputs May 30, 2019 Issued
Array ( [id] => 14844629 [patent_doc_number] => 20190280715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => COMPRESSING ERROR VECTORS FOR DECODING LOGIC TO STORE COMPRESSED IN A DECODER MEMORY USED BY THE DECODING LOGIC [patent_app_type] => utility [patent_app_number] => 16/422891 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422891 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/422891
Compressing error vectors for decoding logic to store compressed in a decoder memory used by the decoding logic May 23, 2019 Issued
Array ( [id] => 14844623 [patent_doc_number] => 20190280712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => REDUCING CONTROL CHANNEL OVERHEAD USING POLAR CODES [patent_app_type] => utility [patent_app_number] => 16/421715 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421715 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/421715
Reducing control channel overhead using polar codes May 23, 2019 Issued
Array ( [id] => 15459119 [patent_doc_number] => 20200042384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => DYNAMIC NEIGHBOR AND BITLINE ASSISTED CORRECTION FOR NAND FLASH STORAGE [patent_app_type] => utility [patent_app_number] => 16/421204 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421204 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/421204
Dynamic neighbor and bitline assisted correction for NAND flash storage May 22, 2019 Issued
Array ( [id] => 16469622 [patent_doc_number] => 20200371159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => DEBUG INTERFACE RECORDER AND REPLAY UNIT [patent_app_type] => utility [patent_app_number] => 16/420362 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420362 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/420362
Debug interface recorder and replay unit May 22, 2019 Issued
Array ( [id] => 16782657 [patent_doc_number] => 20210119736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => COMMUNICATION SYSTEM, CONTROL SYSTEM AND COMMUNICATION DEVICE [patent_app_type] => utility [patent_app_number] => 17/056480 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17056480 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/056480
Communication system for packet data communication, control system for packet data communication and communication device for packet data communication May 21, 2019 Issued
Array ( [id] => 17000627 [patent_doc_number] => 11079431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Entering home state after soft reset signal after address match [patent_app_type] => utility [patent_app_number] => 16/410526 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 46 [patent_no_of_words] => 16303 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/410526
Entering home state after soft reset signal after address match May 12, 2019 Issued
Array ( [id] => 14872555 [patent_doc_number] => 20190286519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => Storing Address of Spare in Failed Memory Location [patent_app_type] => utility [patent_app_number] => 16/405362 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405362 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/405362
Storing address of spare in failed memory location May 6, 2019 Issued
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