Cynthia H. Britt

Array ( [id] => 14448019 [patent_doc_number] => 20190181883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => METHOD FOR GENERATING BASE MATRIX OF LDPC CODE, ENCODING/DECODING METHOD, AND DEVICE [patent_app_type] => utility [patent_app_number] => 16/279551 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14442133 [patent_doc_number] => 20190178939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO [patent_app_type] => utility [patent_app_number] => 16/275015 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16275015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16324919 [patent_doc_number] => 10784900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Rate matching method and apparatus for polar code [patent_app_type] => utility [patent_app_number] => 16/272937 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8424 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16464818 [patent_doc_number] => 10848185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Coding and decoding of polar codes extended to lengths which are not powers of two [patent_app_type] => utility [patent_app_number] => 16/272173 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16594658 [patent_doc_number] => 10903941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Retransmission processing method and apparatus [patent_app_type] => utility [patent_app_number] => 16/272527 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 24869 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16272527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14448213 [patent_doc_number] => 20190181980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => METHOD AND APPARATUS FOR CARRYING IDENTIFICATION INFORMATION [patent_app_type] => utility [patent_app_number] => 16/265224 [patent_app_country] => US [patent_app_date] => 2019-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16265224 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15956931 [patent_doc_number] => 10666386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Transmission method, reception method, transmission device and reception device [patent_app_type] => utility [patent_app_number] => 16/261881 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 31088 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16537311 [patent_doc_number] => 10879932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Encoding method and device, and apparatus [patent_app_type] => utility [patent_app_number] => 16/261220 [patent_app_country] => US [patent_app_date] => 2019-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 14578 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 1507 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16370783 [patent_doc_number] => 10802534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Clock circuitry with fault detection [patent_app_type] => utility [patent_app_number] => 16/256675 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8168 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15701047 [patent_doc_number] => 10606699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Data storage device employing multi-level parity sectors for data recovery procedure [patent_app_type] => utility [patent_app_number] => 16/244426 [patent_app_country] => US [patent_app_date] => 2019-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6517 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16244426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15819095 [patent_doc_number] => 10634721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Test access port, test clock inverter, and shadow access port [patent_app_type] => utility [patent_app_number] => 16/243269 [patent_app_country] => US [patent_app_date] => 2019-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 38 [patent_no_of_words] => 12939 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16243269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14903787 [patent_doc_number] => 20190295659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => MEMORY CONTROLLER AND MEMORY SYSTEM HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 16/238688 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16238688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14217031 [patent_doc_number] => 20190120900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => 3D STACKED DIE TEST ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/229647 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16693062 [patent_doc_number] => 20210075541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => ERROR CORRECTION DEVICE, ERROR CORRECTION METHOD, AND OPTICAL COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 16/955676 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16955676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15819093 [patent_doc_number] => 10634720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => First tap, test compression architecture; second tap, test compression architecture [patent_app_type] => utility [patent_app_number] => 16/225929 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 51 [patent_no_of_words] => 14379 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 457 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16225929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16171546 [patent_doc_number] => 10713116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Solid state device implementing dynamic polar encoding [patent_app_type] => utility [patent_app_number] => 16/211745 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11172 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16211745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16510000 [patent_doc_number] => 20200389256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => ENHANCED HARQ ALGORITHM FOR LARGE ROUND TRIP DELAY LINKS [patent_app_type] => utility [patent_app_number] => 16/767369 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16767369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14021237 [patent_doc_number] => 20190072612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => AT-SPEED TEST ACCESS PORT OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/183347 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16183347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16133865 [patent_doc_number] => 10700711 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-30 [patent_title] => Multi-part upload and editing of erasure-coded objects [patent_app_type] => utility [patent_app_number] => 16/179534 [patent_app_country] => US [patent_app_date] => 2018-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 14751 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16179534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13990211 [patent_doc_number] => 20190064263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM [patent_app_type] => utility [patent_app_number] => 16/175066 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175066 [rel_patent_id] =>[rel_patent_doc_number] =>)