Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16537316 [patent_doc_number] => 10879937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Gel codeword structure encoding and decoding method, apparatus, and related device [patent_app_type] => utility [patent_app_number] => 16/169212 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6404 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169212
Gel codeword structure encoding and decoding method, apparatus, and related device Oct 23, 2018 Issued
Array ( [id] => 15789071 [patent_doc_number] => 10628260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Methods and systems for implementing redundancy in memory controllers [patent_app_type] => utility [patent_app_number] => 16/164730 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16164730 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/164730
Methods and systems for implementing redundancy in memory controllers Oct 17, 2018 Issued
Array ( [id] => 14347431 [patent_doc_number] => 20190155688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => SOFT CHIP-KILL RECOVERY FOR MULTIPLE WORDLINES FAILURE [patent_app_type] => utility [patent_app_number] => 16/151053 [patent_app_country] => US [patent_app_date] => 2018-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16151053 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/151053
Soft chip-kill recovery for multiple wordlines failure Oct 2, 2018 Issued
Array ( [id] => 16651272 [patent_doc_number] => 10928444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Receiving test input message packets and transmitting modulated acknowledgement packets [patent_app_type] => utility [patent_app_number] => 16/150805 [patent_app_country] => US [patent_app_date] => 2018-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 40 [patent_no_of_words] => 12195 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16150805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/150805
Receiving test input message packets and transmitting modulated acknowledgement packets Oct 2, 2018 Issued
Array ( [id] => 15165951 [patent_doc_number] => 10488462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Tap gating scan register, comparator with expected data flip flop [patent_app_type] => utility [patent_app_number] => 16/150744 [patent_app_country] => US [patent_app_date] => 2018-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 73 [patent_no_of_words] => 22041 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16150744 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/150744
Tap gating scan register, comparator with expected data flip flop Oct 2, 2018 Issued
Array ( [id] => 15885391 [patent_doc_number] => 10649032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Core circuitry, tap domain circuitry, separate auxiliary circuitry, output buffers [patent_app_type] => utility [patent_app_number] => 16/148030 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 13370 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148030 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148030
Core circuitry, tap domain circuitry, separate auxiliary circuitry, output buffers Sep 30, 2018 Issued
Array ( [id] => 13849501 [patent_doc_number] => 20190028235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => METHOD AND DEVICE FOR TRANSMITTING AND RECEIVING PACKET IN COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 16/137231 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137231 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137231
Method and device for transmitting and receiving packet in communication system Sep 19, 2018 Issued
Array ( [id] => 17379204 [patent_doc_number] => 11237211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Microchip having a plurality of reconfigurable test structures [patent_app_type] => utility [patent_app_number] => 16/646161 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2758 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16646161 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/646161
Microchip having a plurality of reconfigurable test structures Sep 13, 2018 Issued
Array ( [id] => 16520304 [patent_doc_number] => 10871518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Systems and methods for determining systematic defects [patent_app_type] => utility [patent_app_number] => 16/129433 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16129433 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/129433
Systems and methods for determining systematic defects Sep 11, 2018 Issued
Array ( [id] => 16171543 [patent_doc_number] => 10713113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Solid state drive implementing polar encoding and successive cancellation list decoding [patent_app_type] => utility [patent_app_number] => 16/124034 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10560 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124034 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/124034
Solid state drive implementing polar encoding and successive cancellation list decoding Sep 5, 2018 Issued
Array ( [id] => 14667707 [patent_doc_number] => 10371750 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-06 [patent_title] => Minimization of over-masking in an on product multiple input signature register (OPMISR) [patent_app_type] => utility [patent_app_number] => 16/119605 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119605 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119605
Minimization of over-masking in an on product multiple input signature register (OPMISR) Aug 30, 2018 Issued
Array ( [id] => 14667705 [patent_doc_number] => 10371749 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-06 [patent_title] => Removal of over-masking in an on product multiple input signature register (OPMISR) test [patent_app_type] => utility [patent_app_number] => 16/119458 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119458
Removal of over-masking in an on product multiple input signature register (OPMISR) test Aug 30, 2018 Issued
Array ( [id] => 15699375 [patent_doc_number] => 10605858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Interposer monitor, monitor trigger circuitry having select output and input [patent_app_type] => utility [patent_app_number] => 16/112317 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 50 [patent_no_of_words] => 11370 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112317 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/112317
Interposer monitor, monitor trigger circuitry having select output and input Aug 23, 2018 Issued
Array ( [id] => 13625507 [patent_doc_number] => 20180364305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS [patent_app_type] => utility [patent_app_number] => 16/108761 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16108761 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/108761
Input shift register having parallel serial scan outputs, command output Aug 21, 2018 Issued
Array ( [id] => 13609827 [patent_doc_number] => 20180356463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION [patent_app_type] => utility [patent_app_number] => 16/108274 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16108274 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/108274
Separate output circuitry for tap, additional port, and port selector Aug 21, 2018 Issued
Array ( [id] => 16522120 [patent_doc_number] => 10873347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Channel bit interleaver design for polar coding chain [patent_app_type] => utility [patent_app_number] => 16/055480 [patent_app_country] => US [patent_app_date] => 2018-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 11553 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16055480 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/055480
Channel bit interleaver design for polar coding chain Aug 5, 2018 Issued
Array ( [id] => 16355323 [patent_doc_number] => 10795835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Storage device and interface chip thereof [patent_app_type] => utility [patent_app_number] => 16/053764 [patent_app_country] => US [patent_app_date] => 2018-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11245 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16053764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/053764
Storage device and interface chip thereof Aug 1, 2018 Issued
Array ( [id] => 15981997 [patent_doc_number] => 10671326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Peer to peer health monitoring of dispersed storage units in a distributed storage network [patent_app_type] => utility [patent_app_number] => 16/052126 [patent_app_country] => US [patent_app_date] => 2018-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16052126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/052126
Peer to peer health monitoring of dispersed storage units in a distributed storage network Jul 31, 2018 Issued
Array ( [id] => 14702839 [patent_doc_number] => 10379159 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-08-13 [patent_title] => Minimization of over-masking in an on product multiple input signature register (OPMISR) [patent_app_type] => utility [patent_app_number] => 16/050680 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4815 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050680 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050680
Minimization of over-masking in an on product multiple input signature register (OPMISR) Jul 30, 2018 Issued
Array ( [id] => 15459107 [patent_doc_number] => 20200042378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => Data Dependent Allocation of Error Correction Resources [patent_app_type] => utility [patent_app_number] => 16/051416 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051416 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/051416
Data dependent allocation of error correction resources Jul 30, 2018 Issued
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