
Cynthia H. Britt
Examiner (ID: 11869)
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2117, 2111, 2133, 2138 |
| Total Applications | 1844 |
| Issued Applications | 1687 |
| Pending Applications | 80 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16278976
[patent_doc_number] => 10762007
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-01
[patent_title] => Storage device and interface chip thereof
[patent_app_type] => utility
[patent_app_number] => 16/048348
[patent_app_country] => US
[patent_app_date] => 2018-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 11191
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048348
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/048348 | Storage device and interface chip thereof | Jul 29, 2018 | Issued |
Array
(
[id] => 15397903
[patent_doc_number] => 10539606
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-21
[patent_title] => Stack die gating having test control input, output, and enable
[patent_app_type] => utility
[patent_app_number] => 16/047263
[patent_app_country] => US
[patent_app_date] => 2018-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 24
[patent_no_of_words] => 4986
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047263
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/047263 | Stack die gating having test control input, output, and enable | Jul 26, 2018 | Issued |
Array
(
[id] => 13569097
[patent_doc_number] => 20180336096
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-22
[patent_title] => PERFORMING A DESIRED MANIPULATION OF AN ENCODED DATA SLICE BASED ON A METADATA RESTRICTION AND A STORAGE OPERATIONAL CONDITION
[patent_app_type] => utility
[patent_app_number] => 16/046631
[patent_app_country] => US
[patent_app_date] => 2018-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7109
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 275
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046631
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/046631 | Performing a desired manipulation of an encoded data slice based on a metadata restriction and a storage operational condition | Jul 25, 2018 | Issued |
Array
(
[id] => 13554883
[patent_doc_number] => 20180328989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-15
[patent_title] => INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/043468
[patent_app_country] => US
[patent_app_date] => 2018-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6163
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043468
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/043468 | Shadow protocol circuit producing enable, address, and address control signals | Jul 23, 2018 | Issued |
Array
(
[id] => 16231856
[patent_doc_number] => 10739402
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-11
[patent_title] => Generating multiple pseudo static control signals using on-chip JTAG state machine
[patent_app_type] => utility
[patent_app_number] => 16/039067
[patent_app_country] => US
[patent_app_date] => 2018-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 7930
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039067
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/039067 | Generating multiple pseudo static control signals using on-chip JTAG state machine | Jul 17, 2018 | Issued |
Array
(
[id] => 13972915
[patent_doc_number] => 10215805
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-26
[patent_title] => IC TAP, SAP state machine stepping on TCK falling edge
[patent_app_type] => utility
[patent_app_number] => 16/037649
[patent_app_country] => US
[patent_app_date] => 2018-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 38
[patent_no_of_words] => 12909
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 296
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037649
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/037649 | IC TAP, SAP state machine stepping on TCK falling edge | Jul 16, 2018 | Issued |
Array
(
[id] => 15327013
[patent_doc_number] => 20200003836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-02
[patent_title] => COMPRESSED TEST PATTERNS FOR A FIELD PROGRAMMABLE GATE ARRAY
[patent_app_type] => utility
[patent_app_number] => 16/024722
[patent_app_country] => US
[patent_app_date] => 2018-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8104
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16024722
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/024722 | Compressed test patterns for a field programmable gate array | Jun 28, 2018 | Issued |
Array
(
[id] => 13516115
[patent_doc_number] => 20180309600
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-10-25
[patent_title] => METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING DATA IN A COMMUNICATION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/023692
[patent_app_country] => US
[patent_app_date] => 2018-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16493
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16023692
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/023692 | Method and apparatus for transmitting and receiving data in a communication system | Jun 28, 2018 | Issued |
Array
(
[id] => 13510633
[patent_doc_number] => 20180306859
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-10-25
[patent_title] => INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFFCHIP TAP INTERFACE PORT
[patent_app_type] => utility
[patent_app_number] => 16/022104
[patent_app_country] => US
[patent_app_date] => 2018-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5771
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022104
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/022104 | Integrated circuit with JTAG port, TAP linking module, and off chip TAP interface port | Jun 27, 2018 | Issued |
Array
(
[id] => 18047007
[patent_doc_number] => 11520963
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-06
[patent_title] => System and method for formal fault propagation analysis
[patent_app_type] => utility
[patent_app_number] => 16/620622
[patent_app_country] => US
[patent_app_date] => 2018-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 9041
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16620622
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/620622 | System and method for formal fault propagation analysis | Jun 18, 2018 | Issued |
Array
(
[id] => 14263933
[patent_doc_number] => 10281526
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-05-07
[patent_title] => Device testing architecture, method, and system
[patent_app_type] => utility
[patent_app_number] => 16/003858
[patent_app_country] => US
[patent_app_date] => 2018-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 56
[patent_no_of_words] => 20523
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16003858
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/003858 | Device testing architecture, method, and system | Jun 7, 2018 | Issued |
Array
(
[id] => 13614869
[patent_doc_number] => 20180358985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => POLAR ENCODING AND DECODING USING PREDEFINED INFORMATION
[patent_app_type] => utility
[patent_app_number] => 16/001275
[patent_app_country] => US
[patent_app_date] => 2018-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10333
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001275
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/001275 | Polar encoding and decoding using predefined information | Jun 5, 2018 | Issued |
Array
(
[id] => 15313171
[patent_doc_number] => 10521290
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-31
[patent_title] => Solid state drive with improved LLR tables
[patent_app_type] => utility
[patent_app_number] => 16/000093
[patent_app_country] => US
[patent_app_date] => 2018-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 12929
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 384
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16000093
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/000093 | Solid state drive with improved LLR tables | Jun 4, 2018 | Issued |
Array
(
[id] => 13614871
[patent_doc_number] => 20180358986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => CIRCUITRY AND METHOD FOR DUAL MODE REED-SOLOMON-FORWARD ERROR CORRECTION DECODER
[patent_app_type] => utility
[patent_app_number] => 15/997297
[patent_app_country] => US
[patent_app_date] => 2018-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4199
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15997297
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/997297 | Circuitry and method for dual mode reed-solomon-forward error correction decoder | Jun 3, 2018 | Issued |
Array
(
[id] => 13453455
[patent_doc_number] => 20180278270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-27
[patent_title] => CODING AND DECODING METHOD AND DEVICE, AND SYSTEM
[patent_app_type] => utility
[patent_app_number] => 15/990180
[patent_app_country] => US
[patent_app_date] => 2018-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14938
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15990180
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/990180 | Coding and decoding method and device, and system | May 24, 2018 | Issued |
Array
(
[id] => 14123001
[patent_doc_number] => 10248358
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-02
[patent_title] => Memory component having internal read-modify-write operation
[patent_app_type] => utility
[patent_app_number] => 15/990211
[patent_app_country] => US
[patent_app_date] => 2018-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8503
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15990211
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/990211 | Memory component having internal read-modify-write operation | May 24, 2018 | Issued |
Array
(
[id] => 13567855
[patent_doc_number] => 20180335475
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-22
[patent_title] => Reconfigurable Scan Network Defect Diagnosis
[patent_app_type] => utility
[patent_app_number] => 15/985679
[patent_app_country] => US
[patent_app_date] => 2018-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5220
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15985679
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/985679 | Reconfigurable scan network defect diagnosis | May 20, 2018 | Issued |
Array
(
[id] => 15155713
[patent_doc_number] => 20190356334
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-21
[patent_title] => DATA STORAGE DEVICE EMPLOYING MEMORY EFFICIENT PROCESSING OF UN-CONVERGED CODEWORDS
[patent_app_type] => utility
[patent_app_number] => 15/983033
[patent_app_country] => US
[patent_app_date] => 2018-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4222
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15983033
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/983033 | Data storage device employing memory efficient processing of un-converged codewords | May 16, 2018 | Issued |
Array
(
[id] => 16200694
[patent_doc_number] => 10725857
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-28
[patent_title] => Data storage system for improving data throughput and decode capabilities
[patent_app_type] => utility
[patent_app_number] => 15/980627
[patent_app_country] => US
[patent_app_date] => 2018-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 8575
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980627
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/980627 | Data storage system for improving data throughput and decode capabilities | May 14, 2018 | Issued |
Array
(
[id] => 16537306
[patent_doc_number] => 10879927
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-29
[patent_title] => Compact low density parity check (LDPC) base graph
[patent_app_type] => utility
[patent_app_number] => 15/978678
[patent_app_country] => US
[patent_app_date] => 2018-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 37
[patent_no_of_words] => 8087
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978678
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/978678 | Compact low density parity check (LDPC) base graph | May 13, 2018 | Issued |