Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13350905 [patent_doc_number] => 20180226992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => Offset Lifting Method [patent_app_type] => utility [patent_app_number] => 15/887148 [patent_app_country] => US [patent_app_date] => 2018-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887148 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/887148
Method for generating parity check matrix for low density parity check coding Feb 1, 2018 Issued
Array ( [id] => 16685010 [patent_doc_number] => 10944506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Method and apparatus for transmitting and receiving signal by using polar coding [patent_app_type] => utility [patent_app_number] => 16/483732 [patent_app_country] => US [patent_app_date] => 2018-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12273 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16483732 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/483732
Method and apparatus for transmitting and receiving signal by using polar coding Feb 1, 2018 Issued
Array ( [id] => 12819946 [patent_doc_number] => 20180165154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => DIE-LEVEL MONITORING IN A STORAGE CLUSTER [patent_app_type] => utility [patent_app_number] => 15/882886 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882886 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882886
Die-level monitoring in a storage cluster Jan 28, 2018 Issued
Array ( [id] => 12754246 [patent_doc_number] => 20180143249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST [patent_app_type] => utility [patent_app_number] => 15/875589 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15875589 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/875589
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST Jan 18, 2018 Abandoned
Array ( [id] => 13797377 [patent_doc_number] => 20190012227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => MEMORY SYSTEM AND METHOD FOR OPERATING SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/874261 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/874261
Memory system and method for operating semiconductor memory device Jan 17, 2018 Issued
Array ( [id] => 14982183 [patent_doc_number] => 10445002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Data accessing method, memory controlling circuit unit and memory storage device [patent_app_type] => utility [patent_app_number] => 15/867719 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 10754 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15867719 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/867719
Data accessing method, memory controlling circuit unit and memory storage device Jan 10, 2018 Issued
Array ( [id] => 15819099 [patent_doc_number] => 10634723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Method and system for acquisition of test data [patent_app_type] => utility [patent_app_number] => 15/861570 [patent_app_country] => US [patent_app_date] => 2018-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6018 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15861570 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/861570
Method and system for acquisition of test data Jan 2, 2018 Issued
Array ( [id] => 14739943 [patent_doc_number] => 10389388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Efficient LDPC decoding with predefined iteration-dependent scheduling scheme [patent_app_type] => utility [patent_app_number] => 15/856107 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6713 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15856107 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/856107
Efficient LDPC decoding with predefined iteration-dependent scheduling scheme Dec 27, 2017 Issued
Array ( [id] => 14475023 [patent_doc_number] => 20190189157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => EFFICIENT REWRITE USING LARGER CODEWORD SIZES [patent_app_type] => utility [patent_app_number] => 15/847774 [patent_app_country] => US [patent_app_date] => 2017-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15847774 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/847774
Efficient rewrite using larger codeword sizes Dec 18, 2017 Issued
Array ( [id] => 12645093 [patent_doc_number] => 20180106862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => REDUCED SIGNALING INTERFACE METHOD & APPARATUS [patent_app_type] => utility [patent_app_number] => 15/845282 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845282 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/845282
Tap domain selection circuit with AUX buffers and multiplexer Dec 17, 2017 Issued
Array ( [id] => 14471131 [patent_doc_number] => 20190187208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => MULTIBIT VECTORED SEQUENTIAL WITH SCAN [patent_app_type] => utility [patent_app_number] => 15/846047 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15846047 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/846047
Multibit vectored sequential with scan Dec 17, 2017 Issued
Array ( [id] => 17282560 [patent_doc_number] => 11199586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => JTAG scans through packetization [patent_app_type] => utility [patent_app_number] => 15/837462 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9993 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837462 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837462
JTAG scans through packetization Dec 10, 2017 Issued
Array ( [id] => 13360139 [patent_doc_number] => 20180231609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => IN-FIELD SELF-TEST CONTROLLER FOR SAFETY CRITICAL AUTOMOTIVE USE CASES [patent_app_type] => utility [patent_app_number] => 15/835227 [patent_app_country] => US [patent_app_date] => 2017-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835227 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/835227
In-field self-test controller for safety critical automotive use cases Dec 6, 2017 Issued
Array ( [id] => 14379307 [patent_doc_number] => 20190163566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => UPDATING WRITE-IN-PLACE STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 15/828425 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8707 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15828425 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/828425
Updating write-in-place storage devices Nov 29, 2017 Issued
Array ( [id] => 14523485 [patent_doc_number] => 10339004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Controller and operation method thereof [patent_app_type] => utility [patent_app_number] => 15/826881 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 13055 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826881 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826881
Controller and operation method thereof Nov 29, 2017 Issued
Array ( [id] => 14379305 [patent_doc_number] => 20190163565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => HIGH EFFICIENCY REDUNDANT ARRAY OF INDEPENDENT MEMORY [patent_app_type] => utility [patent_app_number] => 15/827285 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15827285 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/827285
High efficiency redundant array of independent memory Nov 29, 2017 Issued
Array ( [id] => 14601155 [patent_doc_number] => 10353770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Memory system and error correcting method of the same [patent_app_type] => utility [patent_app_number] => 15/826808 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5684 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826808 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826808
Memory system and error correcting method of the same Nov 29, 2017 Issued
Array ( [id] => 14802555 [patent_doc_number] => 10404291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Method and system for error correction in transmitting data using low complexity systematic encoder [patent_app_type] => utility [patent_app_number] => 15/826335 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12630 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826335 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826335
Method and system for error correction in transmitting data using low complexity systematic encoder Nov 28, 2017 Issued
Array ( [id] => 12781108 [patent_doc_number] => 20180152204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => Balanced Reed-Solomon Codes [patent_app_type] => utility [patent_app_number] => 15/824948 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824948 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824948
Balanced Reed-Solomon codes Nov 27, 2017 Issued
Array ( [id] => 13972917 [patent_doc_number] => 10215806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Decompressed/compressed data parallel scan paths with tap decoded shift/scan clocks [patent_app_type] => utility [patent_app_number] => 15/824303 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 45 [patent_no_of_words] => 13679 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824303 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824303
Decompressed/compressed data parallel scan paths with tap decoded shift/scan clocks Nov 27, 2017 Issued
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