Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14986775 [patent_doc_number] => 10447313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Communication method and system with on demand temporal diversity [patent_app_type] => utility [patent_app_number] => 15/824111 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824111 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/824111
Communication method and system with on demand temporal diversity Nov 27, 2017 Issued
Array ( [id] => 16818700 [patent_doc_number] => 11003527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Decoding method and device utilizing flash channel characteristic and data storage system [patent_app_type] => utility [patent_app_number] => 15/822159 [patent_app_country] => US [patent_app_date] => 2017-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3973 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822159 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/822159
Decoding method and device utilizing flash channel characteristic and data storage system Nov 25, 2017 Issued
Array ( [id] => 16818700 [patent_doc_number] => 11003527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Decoding method and device utilizing flash channel characteristic and data storage system [patent_app_type] => utility [patent_app_number] => 15/822159 [patent_app_country] => US [patent_app_date] => 2017-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3973 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822159 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/822159
Decoding method and device utilizing flash channel characteristic and data storage system Nov 25, 2017 Issued
Array ( [id] => 12759619 [patent_doc_number] => 20180145041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SELF-TEST CAPABLE INTEGRATED CIRCUIT APPARATUS AND METHOD OF SELF-TESTING AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/815847 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15815847 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/815847
Self-test capable integrated circuit apparatus and method of self-testing an integrated circuit Nov 16, 2017 Issued
Array ( [id] => 12236796 [patent_doc_number] => 20180069659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'METHOD FOR PROCESSING SIGNALING SUB-SEGMENT, PROCESSING APPARATUS, ACCESS POINT, AND STATION' [patent_app_type] => utility [patent_app_number] => 15/812903 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10221 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812903 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/812903
Method for processing signaling sub-segment, processing apparatus, access point, and station Nov 13, 2017 Issued
Array ( [id] => 16881791 [patent_doc_number] => 11031955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Incremental redundancy and variations for polar codes [patent_app_type] => utility [patent_app_number] => 16/346635 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 12027 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16346635 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/346635
Incremental redundancy and variations for polar codes Nov 9, 2017 Issued
Array ( [id] => 16410800 [patent_doc_number] => 10819372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Method for dividing transport block of LDPC code and apparatus therefor [patent_app_type] => utility [patent_app_number] => 16/347508 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10640 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16347508 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/347508
Method for dividing transport block of LDPC code and apparatus therefor Nov 2, 2017 Issued
Array ( [id] => 14022545 [patent_doc_number] => 20190073266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 15/798418 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798418 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798418
Decoding method, memory storage device and memory control circuit unit Oct 30, 2017 Issued
Array ( [id] => 14233575 [patent_doc_number] => 20190128960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => LOW AREA PARALLEL CHECKER FOR MULTIPLE TEST PATTERNS [patent_app_type] => utility [patent_app_number] => 15/797504 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797504 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797504
Low area parallel checker for multiple test patterns Oct 29, 2017 Issued
Array ( [id] => 14189039 [patent_doc_number] => 20190114225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => DYNAMICALLY ASSIGNING DATA LATCHES [patent_app_type] => utility [patent_app_number] => 15/787700 [patent_app_country] => US [patent_app_date] => 2017-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15787700 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/787700
Combined XOR buffer memory for multiple open blocks of non-volatile memory Oct 17, 2017 Issued
Array ( [id] => 14201493 [patent_doc_number] => 10267855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Tap linking module, first and second taps, input/output linking circuitry [patent_app_type] => utility [patent_app_number] => 15/783365 [patent_app_country] => US [patent_app_date] => 2017-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4243 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15783365 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/783365
Tap linking module, first and second taps, input/output linking circuitry Oct 12, 2017 Issued
Array ( [id] => 14796855 [patent_doc_number] => 10401428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Inverted TCK, input and fixed address registers, comparator, compare register [patent_app_type] => utility [patent_app_number] => 15/724876 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 44 [patent_no_of_words] => 16251 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724876 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724876
Inverted TCK, input and fixed address registers, comparator, compare register Oct 3, 2017 Issued
Array ( [id] => 15549191 [patent_doc_number] => 10574392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => System. methods and devices for transmitting and/or receiving data using an inter communication link [patent_app_type] => utility [patent_app_number] => 15/724150 [patent_app_country] => US [patent_app_date] => 2017-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4360 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724150 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724150
System. methods and devices for transmitting and/or receiving data using an inter communication link Oct 2, 2017 Issued
Array ( [id] => 14107203 [patent_doc_number] => 20190095277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => EFFICIENT TRANSFER OF OBJECTS BETWEEN CONTAINERS ON THE SAME VAULT [patent_app_type] => utility [patent_app_number] => 15/717626 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/717626
Efficient transfer of objects between containers on the same vault Sep 26, 2017 Issued
Array ( [id] => 12152927 [patent_doc_number] => 20180024190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE' [patent_app_type] => utility [patent_app_number] => 15/716029 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9703 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716029 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716029
DDR TMS/TDI, addressable tap, state machine, and tap state monitor Sep 25, 2017 Issued
Array ( [id] => 13512033 [patent_doc_number] => 20180307559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 15/715474 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715474 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715474
Semiconductor devices executing an error scrub operation Sep 25, 2017 Issued
Array ( [id] => 16592573 [patent_doc_number] => 10901836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Systems and methods for mitigating faults in combinatory logic [patent_app_type] => utility [patent_app_number] => 16/326336 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16326336 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/326336
Systems and methods for mitigating faults in combinatory logic Sep 14, 2017 Issued
Array ( [id] => 12688348 [patent_doc_number] => 20180121282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => REGISTER ERROR DETECTION SYSTEM [patent_app_type] => utility [patent_app_number] => 15/705332 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705332 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/705332
Register error detection system Sep 14, 2017 Issued
Array ( [id] => 15058987 [patent_doc_number] => 10459798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Data storage system with multiple parity redundancy [patent_app_type] => utility [patent_app_number] => 15/705452 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705452 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/705452
Data storage system with multiple parity redundancy Sep 14, 2017 Issued
Array ( [id] => 16145727 [patent_doc_number] => 10705934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Scan synchronous-write-through testing architectures for a memory device [patent_app_type] => utility [patent_app_number] => 15/700877 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9677 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700877
Scan synchronous-write-through testing architectures for a memory device Sep 10, 2017 Issued
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