Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11650695 [patent_doc_number] => 20170146596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT' [patent_app_type] => utility [patent_app_number] => 15/402789 [patent_app_country] => US [patent_app_date] => 2017-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6034 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15402789 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/402789
Selectively uncoupling tap and coupling OCI responsive to link instruction Jan 9, 2017 Issued
Array ( [id] => 14559705 [patent_doc_number] => 10348328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Reducing control channel overhead using polar codes [patent_app_type] => utility [patent_app_number] => 15/400512 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400512 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/400512
Reducing control channel overhead using polar codes Jan 5, 2017 Issued
Array ( [id] => 16144147 [patent_doc_number] => 10705142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Device, system and method for providing on-chip test/debug functionality [patent_app_type] => utility [patent_app_number] => 15/394666 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15394666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/394666
Device, system and method for providing on-chip test/debug functionality Dec 28, 2016 Issued
Array ( [id] => 13600061 [patent_doc_number] => 20180351579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => WTRU IDENTIFICATION USING POLAR CODE FROZEN BITS [patent_app_type] => utility [patent_app_number] => 15/780467 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15780467 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/780467
WTRU IDENTIFICATION USING POLAR CODE FROZEN BITS Dec 13, 2016 Abandoned
Array ( [id] => 11530002 [patent_doc_number] => 20170089980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE' [patent_app_type] => utility [patent_app_number] => 15/378903 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9672 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15378903 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/378903
TDI/TMS DDR coupled JTAG domain with 6 preset flip flops Dec 13, 2016 Issued
Array ( [id] => 11693174 [patent_doc_number] => 20170168889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'SEMICONDUCTOR DEVICE, FUNCTIONAL SAFETY SYSTEM AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 15/375644 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13840 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15375644 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/375644
Semiconductor device, functional safety system and program Dec 11, 2016 Issued
Array ( [id] => 11708926 [patent_doc_number] => 20170177425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'STORAGE DEVICE AND READ RECLAIM METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/376227 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 19012 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376227 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/376227
Storage device and read reclaim method thereof Dec 11, 2016 Issued
Array ( [id] => 14007925 [patent_doc_number] => 10222415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Generic width independent parallel checker for a device under test [patent_app_type] => utility [patent_app_number] => 15/375542 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3348 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15375542 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/375542
Generic width independent parallel checker for a device under test Dec 11, 2016 Issued
Array ( [id] => 11500745 [patent_doc_number] => 20170074929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'REDUCED SIGNALING INTERFACE METHOD & APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/358979 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 16818 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15358979 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/358979
Addressable tap domain selection circuit with instruction and linking circuits Nov 21, 2016 Issued
Array ( [id] => 11472872 [patent_doc_number] => 20170059655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 15/352792 [patent_app_country] => US [patent_app_date] => 2016-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 14828 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15352792 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/352792
TDI, SC, and SE gating circuitry with count complete input Nov 15, 2016 Issued
Array ( [id] => 14149247 [patent_doc_number] => 10255004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Systems and methods for managing address-mapping data in memory devices [patent_app_type] => utility [patent_app_number] => 15/349063 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4352 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349063 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/349063
Systems and methods for managing address-mapping data in memory devices Nov 10, 2016 Issued
Array ( [id] => 13179405 [patent_doc_number] => 10105189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Techniques for correcting an error in a nonvolatile memory of an embedded component for an end effector in a robotic surgical system [patent_app_type] => utility [patent_app_number] => 15/348443 [patent_app_country] => US [patent_app_date] => 2016-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5404 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15348443 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/348443
Techniques for correcting an error in a nonvolatile memory of an embedded component for an end effector in a robotic surgical system Nov 9, 2016 Issued
Array ( [id] => 13084759 [patent_doc_number] => 10062451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Background memory test apparatus and methods [patent_app_type] => utility [patent_app_number] => 15/346737 [patent_app_country] => US [patent_app_date] => 2016-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15346737 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/346737
Background memory test apparatus and methods Nov 8, 2016 Issued
Array ( [id] => 11472869 [patent_doc_number] => 20170059652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'OPTIMIZED JTAG INTERFACE' [patent_app_type] => utility [patent_app_number] => 15/347323 [patent_app_country] => US [patent_app_date] => 2016-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14868 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15347323 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/347323
Tap SPC with tap state machine reset and clock control Nov 8, 2016 Issued
Array ( [id] => 12711133 [patent_doc_number] => 20180128877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => Methods and Apparatus for Test Insertion Points [patent_app_type] => utility [patent_app_number] => 15/347619 [patent_app_country] => US [patent_app_date] => 2016-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15347619 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/347619
Methods and apparatus for test insertion points Nov 8, 2016 Issued
Array ( [id] => 11458320 [patent_doc_number] => 20170052226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'DIRECT SCAN ACCESS JTAG' [patent_app_type] => utility [patent_app_number] => 15/346110 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13945 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15346110 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/346110
TAP and auxiliary circuitry with auxiliary output multiplexer and buffers Nov 7, 2016 Issued
Array ( [id] => 11444560 [patent_doc_number] => 20170045581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => '3D STACKED DIE TEST ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/340507 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7045 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340507
Tap dual port router circuitry with gated shiftDR and clockDR Oct 31, 2016 Issued
Array ( [id] => 11845757 [patent_doc_number] => 09733308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Tap, CMD with two flip-flops, routing circuit, and data register' [patent_app_type] => utility [patent_app_number] => 15/336101 [patent_app_country] => US [patent_app_date] => 2016-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 43 [patent_no_of_words] => 13175 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15336101 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/336101
Tap, CMD with two flip-flops, routing circuit, and data register Oct 26, 2016 Issued
Array ( [id] => 13157731 [patent_doc_number] => 10095591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Test circuit for 3D semiconductor device and method for testing thereof [patent_app_type] => utility [patent_app_number] => 15/291172 [patent_app_country] => US [patent_app_date] => 2016-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4550 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15291172 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/291172
Test circuit for 3D semiconductor device and method for testing thereof Oct 11, 2016 Issued
Array ( [id] => 14065395 [patent_doc_number] => 10237015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Transmission method, reception method, transmission device and reception device [patent_app_type] => utility [patent_app_number] => 15/284601 [patent_app_country] => US [patent_app_date] => 2016-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 30532 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15284601 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/284601
Transmission method, reception method, transmission device and reception device Oct 3, 2016 Issued
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