Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13156317 [patent_doc_number] => 10094876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking [patent_app_type] => utility [patent_app_number] => 15/284070 [patent_app_country] => US [patent_app_date] => 2016-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15284070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/284070
On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking Oct 2, 2016 Issued
Array ( [id] => 11398672 [patent_doc_number] => 20170019210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'Adaptive Modulation and Coding Method, Apparatus, and System' [patent_app_type] => utility [patent_app_number] => 15/281985 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281985 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/281985
Adaptive modulation and coding method, apparatus, and system Sep 29, 2016 Issued
Array ( [id] => 11396421 [patent_doc_number] => 20170016957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION' [patent_app_type] => utility [patent_app_number] => 15/278733 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9536 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15278733 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/278733
Selectable separate scan paths with hold state multiplexer and adapter Sep 27, 2016 Issued
Array ( [id] => 13242553 [patent_doc_number] => 10134483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Centralized built-in soft-repair architecture for integrated circuits with embedded memories [patent_app_type] => utility [patent_app_number] => 15/275694 [patent_app_country] => US [patent_app_date] => 2016-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10276 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15275694 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/275694
Centralized built-in soft-repair architecture for integrated circuits with embedded memories Sep 25, 2016 Issued
Array ( [id] => 11531055 [patent_doc_number] => 20170091033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'CONSIDERING OBJECT HEALTH OF A MULTI-REGION OBJECT' [patent_app_type] => utility [patent_app_number] => 15/272968 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272968 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272968
Considering object health of a multi-region object Sep 21, 2016 Issued
Array ( [id] => 11384270 [patent_doc_number] => 20170010326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION' [patent_app_type] => utility [patent_app_number] => 15/270746 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13548 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270746 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270746
Low power scan path cells with hold state multiplexer circuitry Sep 19, 2016 Issued
Array ( [id] => 13807223 [patent_doc_number] => 10180878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Memory system for recording data and memory control method for recording data [patent_app_type] => utility [patent_app_number] => 15/262346 [patent_app_country] => US [patent_app_date] => 2016-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 13782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15262346 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/262346
Memory system for recording data and memory control method for recording data Sep 11, 2016 Issued
Array ( [id] => 12331809 [patent_doc_number] => 09946597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Protecting embedded nonvolatile memory from interference [patent_app_type] => utility [patent_app_number] => 15/256591 [patent_app_country] => US [patent_app_date] => 2016-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5868 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15256591 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/256591
Protecting embedded nonvolatile memory from interference Sep 3, 2016 Issued
Array ( [id] => 13350917 [patent_doc_number] => 20180226998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => METHOD AND DEVICE AND COMPUTER PROGRAM FOR DEMODULATING RECEIVED SYMBOLS USING TURBO-DEMODULATION SCHEME [patent_app_type] => utility [patent_app_number] => 15/749242 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15749242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/749242
Method and device and computer program for demodulating received symbols using turbo-demodulation scheme Aug 30, 2016 Issued
Array ( [id] => 15700689 [patent_doc_number] => 10606520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Methods and apparatus to read from a nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 15/253470 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253470 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/253470
Methods and apparatus to read from a nonvolatile memory device Aug 30, 2016 Issued
Array ( [id] => 12536541 [patent_doc_number] => 10009045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Decoding method, memory controlling circuit unit and memory storage device [patent_app_type] => utility [patent_app_number] => 15/242605 [patent_app_country] => US [patent_app_date] => 2016-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 9904 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15242605 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/242605
Decoding method, memory controlling circuit unit and memory storage device Aug 21, 2016 Issued
Array ( [id] => 12018043 [patent_doc_number] => 09810740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'DAP local, group, and global control of TAP TCK' [patent_app_type] => utility [patent_app_number] => 15/235912 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 44 [patent_no_of_words] => 16496 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235912 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/235912
DAP local, group, and global control of TAP TCK Aug 11, 2016 Issued
Array ( [id] => 11810414 [patent_doc_number] => 09714980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Scan testing scan frames with embedded commands and differential signaling' [patent_app_type] => utility [patent_app_number] => 15/233280 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 9743 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15233280 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/233280
Scan testing scan frames with embedded commands and differential signaling Aug 9, 2016 Issued
Array ( [id] => 11874750 [patent_doc_number] => 09746517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'IC interposer with TAP controller and output boundary scan cell' [patent_app_type] => utility [patent_app_number] => 15/227536 [patent_app_country] => US [patent_app_date] => 2016-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 66 [patent_no_of_words] => 14478 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15227536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/227536
IC interposer with TAP controller and output boundary scan cell Aug 2, 2016 Issued
Array ( [id] => 13081831 [patent_doc_number] => 10060979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Generating multiple pseudo static control signals using on-chip JTAG state machine [patent_app_type] => utility [patent_app_number] => 15/226898 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7899 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15226898 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/226898
Generating multiple pseudo static control signals using on-chip JTAG state machine Aug 1, 2016 Issued
Array ( [id] => 12230347 [patent_doc_number] => 09917601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Adaptive error correction in a memory system' [patent_app_type] => utility [patent_app_number] => 15/226160 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6798 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15226160 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/226160
Adaptive error correction in a memory system Aug 1, 2016 Issued
Array ( [id] => 13681907 [patent_doc_number] => 20160379690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE [patent_app_type] => utility [patent_app_number] => 15/225717 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225717 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225717
ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE Jul 31, 2016 Abandoned
Array ( [id] => 13171905 [patent_doc_number] => 10102067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Performing a desired manipulation of an encoded data slice based on a metadata restriction and a storage operational condition [patent_app_type] => utility [patent_app_number] => 15/210162 [patent_app_country] => US [patent_app_date] => 2016-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7030 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 399 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15210162 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/210162
Performing a desired manipulation of an encoded data slice based on a metadata restriction and a storage operational condition Jul 13, 2016 Issued
Array ( [id] => 12060762 [patent_doc_number] => 20170337106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT' [patent_app_type] => utility [patent_app_number] => 15/208618 [patent_app_country] => US [patent_app_date] => 2016-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12523 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208618 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/208618
Decoding method, memory storage device and memory control circuit unit Jul 12, 2016 Issued
Array ( [id] => 11423612 [patent_doc_number] => 20170031756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/209043 [patent_app_country] => US [patent_app_date] => 2016-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9796 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209043 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/209043
Semiconductor memory devices having input/output gating circuit and memory systems including the same Jul 12, 2016 Issued
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