Search

Cynthia H. Britt

Examiner (ID: 18558, Phone: (571)272-3815 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2133, 2138, 2117, 2111
Total Applications
1856
Issued Applications
1695
Pending Applications
82
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13199319 [patent_doc_number] => 10114578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Solid state disk and data moving method [patent_app_type] => utility [patent_app_number] => 15/192614 [patent_app_country] => US [patent_app_date] => 2016-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192614 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/192614
Solid state disk and data moving method Jun 23, 2016 Issued
Array ( [id] => 11458321 [patent_doc_number] => 20170052227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST' [patent_app_type] => utility [patent_app_number] => 15/188786 [patent_app_country] => US [patent_app_date] => 2016-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15188786 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/188786
Selective per-cycle masking of scan chains for system level test Jun 20, 2016 Issued
Array ( [id] => 13081829 [patent_doc_number] => 10060978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Implementing prioritized compressed failure defects for efficient scan diagnostics [patent_app_type] => utility [patent_app_number] => 15/188593 [patent_app_country] => US [patent_app_date] => 2016-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15188593 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/188593
Implementing prioritized compressed failure defects for efficient scan diagnostics Jun 20, 2016 Issued
Array ( [id] => 13705459 [patent_doc_number] => 20170363684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => BITWISE ROTATING SCAN SECTION FOR MICROELECTRONIC CHIP TESTING AND DIAGNOSTICS [patent_app_type] => utility [patent_app_number] => 15/188386 [patent_app_country] => US [patent_app_date] => 2016-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15188386 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/188386
Bitwise rotating scan section for microelectronic chip testing and diagnostics Jun 20, 2016 Issued
Array ( [id] => 16610046 [patent_doc_number] => 10911071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Apparatus, method and system to support codes with variable codeword lengths and information lengths [patent_app_type] => utility [patent_app_number] => 16/074521 [patent_app_country] => US [patent_app_date] => 2016-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12125 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16074521 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/074521
Apparatus, method and system to support codes with variable codeword lengths and information lengths Jun 12, 2016 Issued
Array ( [id] => 12474999 [patent_doc_number] => 09990251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Semiconductor system with a column control circuit [patent_app_type] => utility [patent_app_number] => 15/175408 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10575 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15175408 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/175408
Semiconductor system with a column control circuit Jun 6, 2016 Issued
Array ( [id] => 11085445 [patent_doc_number] => 20160282410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION' [patent_app_type] => utility [patent_app_number] => 15/174341 [patent_app_country] => US [patent_app_date] => 2016-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 17856 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15174341 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/174341
TAPs and TAP selector output enables coupled to output circuitry Jun 5, 2016 Issued
Array ( [id] => 11088508 [patent_doc_number] => 20160285476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'METHOD FOR ENCODING AND DECODING OF DATA BASED ON BINARY REED-SOLOMON CODES' [patent_app_type] => utility [patent_app_number] => 15/173712 [patent_app_country] => US [patent_app_date] => 2016-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4741 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15173712 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/173712
METHOD FOR ENCODING AND DECODING OF DATA BASED ON BINARY REED-SOLOMON CODES Jun 4, 2016 Abandoned
Array ( [id] => 12480174 [patent_doc_number] => 09991989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Soft hybrid automatic repeat request [patent_app_type] => utility [patent_app_number] => 15/173206 [patent_app_country] => US [patent_app_date] => 2016-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12932 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15173206 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/173206
Soft hybrid automatic repeat request Jun 2, 2016 Issued
Array ( [id] => 11077222 [patent_doc_number] => 20160274186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS' [patent_app_type] => utility [patent_app_number] => 15/169023 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9270 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169023 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/169023
Core wrappers, I/O circuitry, link instruction register with and gate May 30, 2016 Issued
Array ( [id] => 14739939 [patent_doc_number] => 10389386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Data processing apparatus, data processing method, and program [patent_app_type] => utility [patent_app_number] => 15/577486 [patent_app_country] => US [patent_app_date] => 2016-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3769 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15577486 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/577486
Data processing apparatus, data processing method, and program May 26, 2016 Issued
Array ( [id] => 11062041 [patent_doc_number] => 20160259003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES' [patent_app_type] => utility [patent_app_number] => 15/159171 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6237 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15159171 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/159171
Full/reduced pin JTAG interface shadow protocol detection, command, address circuits May 18, 2016 Issued
Array ( [id] => 11055612 [patent_doc_number] => 20160252574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO' [patent_app_type] => utility [patent_app_number] => 15/151035 [patent_app_country] => US [patent_app_date] => 2016-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14013 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15151035 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/151035
Decompressed/compressed data parallel scan paths with input/output shift register, SCI/SCO May 9, 2016 Issued
Array ( [id] => 12803161 [patent_doc_number] => 20180159557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => CODING DEVICE AND CODING METHOD [patent_app_type] => utility [patent_app_number] => 15/570815 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15570815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/570815
Coding device and coding method for a DVB-like LDPC code and a LDPC code in an ETRI format May 5, 2016 Issued
Array ( [id] => 12038840 [patent_doc_number] => 09817070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Third tap circuitry controlling linking first and second tap circuitry' [patent_app_type] => utility [patent_app_number] => 15/134877 [patent_app_country] => US [patent_app_date] => 2016-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4492 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/134877
Third tap circuitry controlling linking first and second tap circuitry Apr 20, 2016 Issued
Array ( [id] => 11036937 [patent_doc_number] => 20160233894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM' [patent_app_type] => utility [patent_app_number] => 15/132143 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132143 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/132143
Reduced complexity non-binary LDPC decoding algorithm Apr 17, 2016 Issued
Array ( [id] => 11037021 [patent_doc_number] => 20160233977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'USER EQUIPMENT USING HYBRID AUTOMATIC REPEAT REQUEST' [patent_app_type] => utility [patent_app_number] => 15/132096 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2753 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132096 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/132096
User equipment using hybrid automatic repeat request Apr 17, 2016 Issued
Array ( [id] => 13041187 [patent_doc_number] => 10042729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Apparatus and method for a scalable test engine [patent_app_type] => utility [patent_app_number] => 15/089448 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9115 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089448 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/089448
Apparatus and method for a scalable test engine Mar 31, 2016 Issued
Array ( [id] => 11982042 [patent_doc_number] => 20170286197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'VALIDATION OF MEMORY ON-DIE ERROR CORRECTION CODE' [patent_app_type] => utility [patent_app_number] => 15/089316 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7753 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089316 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/089316
Validation of memory on-die error correction code Mar 31, 2016 Issued
Array ( [id] => 11481640 [patent_doc_number] => 09588178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Parallel and serial data with controller, delay, and register circuits' [patent_app_type] => utility [patent_app_number] => 15/075950 [patent_app_country] => US [patent_app_date] => 2016-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 15495 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15075950 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/075950
Parallel and serial data with controller, delay, and register circuits Mar 20, 2016 Issued
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