
Cynthia H. Britt
Examiner (ID: 11869)
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2117, 2111, 2133, 2138 |
| Total Applications | 1844 |
| Issued Applications | 1687 |
| Pending Applications | 80 |
| Abandoned Applications | 105 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11126089
[patent_doc_number] => 20160323064
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-03
[patent_title] => 'TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD'
[patent_app_type] => utility
[patent_app_number] => 15/206270
[patent_app_country] => US
[patent_app_date] => 2016-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 12030
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15206270
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/206270 | Transmission device, transmission method, reception device, and reception method | Jul 9, 2016 | Issued |
Array
(
[id] => 11860151
[patent_doc_number] => 09739832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-22
[patent_title] => 'Test messaging demodulate and modulate on separate power pads'
[patent_app_type] => utility
[patent_app_number] => 15/205527
[patent_app_country] => US
[patent_app_date] => 2016-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 39
[patent_no_of_words] => 12694
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15205527
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/205527 | Test messaging demodulate and modulate on separate power pads | Jul 7, 2016 | Issued |
Array
(
[id] => 11116427
[patent_doc_number] => 20160313401
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-27
[patent_title] => 'PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO'
[patent_app_type] => utility
[patent_app_number] => 15/203363
[patent_app_country] => US
[patent_app_date] => 2016-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 14006
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15203363
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/203363 | IC and process shifting compressed data and loading scan paths | Jul 5, 2016 | Issued |
Array
(
[id] => 11116426
[patent_doc_number] => 20160313400
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-27
[patent_title] => 'PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO'
[patent_app_type] => utility
[patent_app_number] => 15/203333
[patent_app_country] => US
[patent_app_date] => 2016-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 14003
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15203333
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/203333 | Tap controller state machine scanning capturing plurality of scan paths | Jul 5, 2016 | Issued |
Array
(
[id] => 11118661
[patent_doc_number] => 20160315634
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-27
[patent_title] => 'CRC CALCULATION METHOD, AND APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 15/199222
[patent_app_country] => US
[patent_app_date] => 2016-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 16111
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199222
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/199222 | CRC calculation method, and apparatus | Jun 29, 2016 | Issued |
Array
(
[id] => 13244701
[patent_doc_number] => 10135571
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-20
[patent_title] => Polar code processing method and system, and wireless communications apparatus
[patent_app_type] => utility
[patent_app_number] => 15/196708
[patent_app_country] => US
[patent_app_date] => 2016-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6686
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15196708
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/196708 | Polar code processing method and system, and wireless communications apparatus | Jun 28, 2016 | Issued |
Array
(
[id] => 13002503
[patent_doc_number] => 10024914
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-17
[patent_title] => Diagnosing failure locations of an integrated circuit with logic built-in self-test
[patent_app_type] => utility
[patent_app_number] => 15/196915
[patent_app_country] => US
[patent_app_date] => 2016-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4690
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15196915
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/196915 | Diagnosing failure locations of an integrated circuit with logic built-in self-test | Jun 28, 2016 | Issued |
Array
(
[id] => 13083163
[patent_doc_number] => 10061648
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-08-28
[patent_title] => Efficient method for redundant storage of a set of encoded data slices
[patent_app_type] => utility
[patent_app_number] => 15/195252
[patent_app_country] => US
[patent_app_date] => 2016-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 6839
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195252
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/195252 | Efficient method for redundant storage of a set of encoded data slices | Jun 27, 2016 | Issued |
Array
(
[id] => 13199319
[patent_doc_number] => 10114578
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-30
[patent_title] => Solid state disk and data moving method
[patent_app_type] => utility
[patent_app_number] => 15/192614
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 6513
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15192614
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/192614 | Solid state disk and data moving method | Jun 23, 2016 | Issued |
Array
(
[id] => 13677887
[patent_doc_number] => 20160377677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-29
[patent_title] => CHIP AND METHOD FOR TESTING A PROCESSING COMPONENT OF A CHIP
[patent_app_type] => utility
[patent_app_number] => 15/191553
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4644
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191553
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/191553 | CHIP AND METHOD FOR TESTING A PROCESSING COMPONENT OF A CHIP | Jun 23, 2016 | Abandoned |
Array
(
[id] => 13081829
[patent_doc_number] => 10060978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-08-28
[patent_title] => Implementing prioritized compressed failure defects for efficient scan diagnostics
[patent_app_type] => utility
[patent_app_number] => 15/188593
[patent_app_country] => US
[patent_app_date] => 2016-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7446
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15188593
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/188593 | Implementing prioritized compressed failure defects for efficient scan diagnostics | Jun 20, 2016 | Issued |
Array
(
[id] => 11458321
[patent_doc_number] => 20170052227
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST'
[patent_app_type] => utility
[patent_app_number] => 15/188786
[patent_app_country] => US
[patent_app_date] => 2016-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7127
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15188786
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/188786 | Selective per-cycle masking of scan chains for system level test | Jun 20, 2016 | Issued |
Array
(
[id] => 13705459
[patent_doc_number] => 20170363684
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-21
[patent_title] => BITWISE ROTATING SCAN SECTION FOR MICROELECTRONIC CHIP TESTING AND DIAGNOSTICS
[patent_app_type] => utility
[patent_app_number] => 15/188386
[patent_app_country] => US
[patent_app_date] => 2016-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5708
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15188386
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/188386 | Bitwise rotating scan section for microelectronic chip testing and diagnostics | Jun 20, 2016 | Issued |
Array
(
[id] => 16610046
[patent_doc_number] => 10911071
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-02
[patent_title] => Apparatus, method and system to support codes with variable codeword lengths and information lengths
[patent_app_type] => utility
[patent_app_number] => 16/074521
[patent_app_country] => US
[patent_app_date] => 2016-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 12125
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16074521
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/074521 | Apparatus, method and system to support codes with variable codeword lengths and information lengths | Jun 12, 2016 | Issued |
Array
(
[id] => 12474999
[patent_doc_number] => 09990251
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-05
[patent_title] => Semiconductor system with a column control circuit
[patent_app_type] => utility
[patent_app_number] => 15/175408
[patent_app_country] => US
[patent_app_date] => 2016-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10575
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15175408
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/175408 | Semiconductor system with a column control circuit | Jun 6, 2016 | Issued |
Array
(
[id] => 11085445
[patent_doc_number] => 20160282410
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-29
[patent_title] => 'METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION'
[patent_app_type] => utility
[patent_app_number] => 15/174341
[patent_app_country] => US
[patent_app_date] => 2016-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 17856
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15174341
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/174341 | TAPs and TAP selector output enables coupled to output circuitry | Jun 5, 2016 | Issued |
Array
(
[id] => 11088508
[patent_doc_number] => 20160285476
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-29
[patent_title] => 'METHOD FOR ENCODING AND DECODING OF DATA BASED ON BINARY REED-SOLOMON CODES'
[patent_app_type] => utility
[patent_app_number] => 15/173712
[patent_app_country] => US
[patent_app_date] => 2016-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4741
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15173712
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/173712 | METHOD FOR ENCODING AND DECODING OF DATA BASED ON BINARY REED-SOLOMON CODES | Jun 4, 2016 | Abandoned |
Array
(
[id] => 12480174
[patent_doc_number] => 09991989
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-05
[patent_title] => Soft hybrid automatic repeat request
[patent_app_type] => utility
[patent_app_number] => 15/173206
[patent_app_country] => US
[patent_app_date] => 2016-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 12932
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15173206
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/173206 | Soft hybrid automatic repeat request | Jun 2, 2016 | Issued |
Array
(
[id] => 11077222
[patent_doc_number] => 20160274186
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-22
[patent_title] => 'INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS'
[patent_app_type] => utility
[patent_app_number] => 15/169023
[patent_app_country] => US
[patent_app_date] => 2016-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 9270
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169023
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/169023 | Core wrappers, I/O circuitry, link instruction register with and gate | May 30, 2016 | Issued |
Array
(
[id] => 14739939
[patent_doc_number] => 10389386
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-20
[patent_title] => Data processing apparatus, data processing method, and program
[patent_app_type] => utility
[patent_app_number] => 15/577486
[patent_app_country] => US
[patent_app_date] => 2016-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 3769
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15577486
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/577486 | Data processing apparatus, data processing method, and program | May 26, 2016 | Issued |