Search

Cynthia H. Britt

Examiner (ID: 11869)

Most Active Art Unit
2117
Art Unit(s)
2117, 2111, 2133, 2138
Total Applications
1844
Issued Applications
1687
Pending Applications
80
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11062041 [patent_doc_number] => 20160259003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES' [patent_app_type] => utility [patent_app_number] => 15/159171 [patent_app_country] => US [patent_app_date] => 2016-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6237 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15159171 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/159171
Full/reduced pin JTAG interface shadow protocol detection, command, address circuits May 18, 2016 Issued
Array ( [id] => 11055612 [patent_doc_number] => 20160252574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO' [patent_app_type] => utility [patent_app_number] => 15/151035 [patent_app_country] => US [patent_app_date] => 2016-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14013 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15151035 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/151035
Decompressed/compressed data parallel scan paths with input/output shift register, SCI/SCO May 9, 2016 Issued
Array ( [id] => 12803161 [patent_doc_number] => 20180159557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => CODING DEVICE AND CODING METHOD [patent_app_type] => utility [patent_app_number] => 15/570815 [patent_app_country] => US [patent_app_date] => 2016-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15570815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/570815
Coding device and coding method for a DVB-like LDPC code and a LDPC code in an ETRI format May 5, 2016 Issued
Array ( [id] => 12038840 [patent_doc_number] => 09817070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Third tap circuitry controlling linking first and second tap circuitry' [patent_app_type] => utility [patent_app_number] => 15/134877 [patent_app_country] => US [patent_app_date] => 2016-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4492 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15134877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/134877
Third tap circuitry controlling linking first and second tap circuitry Apr 20, 2016 Issued
Array ( [id] => 11036937 [patent_doc_number] => 20160233894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM' [patent_app_type] => utility [patent_app_number] => 15/132143 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132143 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/132143
Reduced complexity non-binary LDPC decoding algorithm Apr 17, 2016 Issued
Array ( [id] => 11037021 [patent_doc_number] => 20160233977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'USER EQUIPMENT USING HYBRID AUTOMATIC REPEAT REQUEST' [patent_app_type] => utility [patent_app_number] => 15/132096 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2753 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132096 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/132096
User equipment using hybrid automatic repeat request Apr 17, 2016 Issued
Array ( [id] => 13041187 [patent_doc_number] => 10042729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Apparatus and method for a scalable test engine [patent_app_type] => utility [patent_app_number] => 15/089448 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9115 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089448 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/089448
Apparatus and method for a scalable test engine Mar 31, 2016 Issued
Array ( [id] => 11982042 [patent_doc_number] => 20170286197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'VALIDATION OF MEMORY ON-DIE ERROR CORRECTION CODE' [patent_app_type] => utility [patent_app_number] => 15/089316 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7753 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089316 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/089316
Validation of memory on-die error correction code Mar 31, 2016 Issued
Array ( [id] => 11481640 [patent_doc_number] => 09588178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Parallel and serial data with controller, delay, and register circuits' [patent_app_type] => utility [patent_app_number] => 15/075950 [patent_app_country] => US [patent_app_date] => 2016-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 15495 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15075950 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/075950
Parallel and serial data with controller, delay, and register circuits Mar 20, 2016 Issued
Array ( [id] => 11759261 [patent_doc_number] => 20170206130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT' [patent_app_type] => utility [patent_app_number] => 15/068663 [patent_app_country] => US [patent_app_date] => 2016-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10330 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15068663 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/068663
Decoding method, memory storage device and memory control circuit unit Mar 13, 2016 Issued
Array ( [id] => 13202807 [patent_doc_number] => 10116331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Data transmitting and receiving apparatus having improved low-density parity-check (LDPC) encoding, decoding and transmission rate [patent_app_type] => utility [patent_app_number] => 15/067388 [patent_app_country] => US [patent_app_date] => 2016-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7034 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15067388 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/067388
Data transmitting and receiving apparatus having improved low-density parity-check (LDPC) encoding, decoding and transmission rate Mar 10, 2016 Issued
Array ( [id] => 15642835 [patent_doc_number] => 10594435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Signalling coding and modulation method and demodulation and decoding method and device [patent_app_type] => utility [patent_app_number] => 15/558184 [patent_app_country] => US [patent_app_date] => 2016-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8574 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15558184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/558184
Signalling coding and modulation method and demodulation and decoding method and device Mar 10, 2016 Issued
Array ( [id] => 12213289 [patent_doc_number] => 09910090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Bypassing an encoded latch on a chip during a test-pattern scan' [patent_app_type] => utility [patent_app_number] => 15/063772 [patent_app_country] => US [patent_app_date] => 2016-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5229 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15063772 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/063772
Bypassing an encoded latch on a chip during a test-pattern scan Mar 7, 2016 Issued
Array ( [id] => 11957404 [patent_doc_number] => 20170261556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'CLOCK PATH TECHNIQUE FOR USING ON-CHIP CIRCUITRY TO GENERATE A CORRECT ENCODE PATTERN TO TEST THE ON-CHIP CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 15/063953 [patent_app_country] => US [patent_app_date] => 2016-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5216 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15063953 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/063953
Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry Mar 7, 2016 Issued
Array ( [id] => 10981754 [patent_doc_number] => 20160178697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'SCAN TEST METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/058719 [patent_app_country] => US [patent_app_date] => 2016-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 22251 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058719 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/058719
Tap clock and enable control of scan register, flip-flop, compressor Mar 1, 2016 Issued
Array ( [id] => 11860154 [patent_doc_number] => 09739834 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-22 [patent_title] => 'System and method for transferring serialized test result data from a system on a chip' [patent_app_type] => utility [patent_app_number] => 15/051714 [patent_app_country] => US [patent_app_date] => 2016-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8872 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051714 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/051714
System and method for transferring serialized test result data from a system on a chip Feb 23, 2016 Issued
Array ( [id] => 12289443 [patent_doc_number] => 09933485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Deterministic built-in self-test based on compressed test patterns stored on chip and their derivatives [patent_app_type] => utility [patent_app_number] => 15/051063 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051063 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/051063
Deterministic built-in self-test based on compressed test patterns stored on chip and their derivatives Feb 22, 2016 Issued
Array ( [id] => 11658469 [patent_doc_number] => 09671462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'TAM, controller, selector, scan router, external data and control buses' [patent_app_type] => utility [patent_app_number] => 15/015885 [patent_app_country] => US [patent_app_date] => 2016-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 56 [patent_no_of_words] => 20929 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15015885 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/015885
TAM, controller, selector, scan router, external data and control buses Feb 3, 2016 Issued
Array ( [id] => 10785552 [patent_doc_number] => 20160131707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'MULTIPLE-CAPTURE DFT METHOD FOR DETECTING OR LOCATING CROSSING CLOCK-DOMAIN FAULTS DURING SELF-TEST OR SCAN-TEST' [patent_app_type] => utility [patent_app_number] => 15/000713 [patent_app_country] => US [patent_app_date] => 2016-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 15498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15000713 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/000713
Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test Jan 18, 2016 Issued
Array ( [id] => 11751618 [patent_doc_number] => 09709627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Interposer with TAP, trigger, address/data bus, and analog monitor circuitry' [patent_app_type] => utility [patent_app_number] => 14/989325 [patent_app_country] => US [patent_app_date] => 2016-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 50 [patent_no_of_words] => 11509 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14989325 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/989325
Interposer with TAP, trigger, address/data bus, and analog monitor circuitry Jan 5, 2016 Issued
Menu